David M. Bull
According to our database1,
David M. Bull
authored at least 21 papers
between 2008 and 2019.
Collaborative distances:
Collaborative distances:
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Bibliography
2019
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019
2017
Power Integrity Analysis of a 28 nm Dual-Core ARM Cortex-A57 Cluster Using an All-Digital Power Delivery Monitor.
IEEE J. Solid State Circuits, 2017
2015
Proceedings of the Symposium on VLSI Circuits, 2015
14.6 An all-digital power-delivery monitor for analysis of a 28nm dual-core ARM Cortex-A57 cluster.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Analysis of adaptive clocking technique for resonant supply voltage noise mitigation.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015
2014
A 1 GHz Hardware Loop-Accelerator With Razor-Based Dynamic Adaptation for Energy-Efficient Operation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
A Low-Power 1-GHz Razor FIR Accelerator With Time-Borrow Tracking Pipeline and Approximate Error Correction in 65-nm CMOS.
IEEE J. Solid State Circuits, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
A low-power 1GHz razor FIR accelerator with time-borrow tracking pipeline and approximate error correction in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 1GHz hardware loop-accelerator with razor-based dynamic adaptation for energy-efficient operation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Correction to "A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation".
IEEE J. Solid State Circuits, 2011
A Power-Efficient 32 bit ARM Processor Using Timing-Error Detection and Correction for Transient-Error Tolerance and Adaptation to PVT Variation.
IEEE J. Solid State Circuits, 2011
Proceedings of the 48th Design Automation Conference, 2011
2010
A power-efficient 32b ARM ISA processor using timing-error detection and correction for transient-error tolerance and adaptation to PVT variation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
IEEE J. Solid State Circuits, 2009
Proceedings of the 46th Design Automation Conference, 2009
2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 45th Design Automation Conference, 2008