Katsuhiko Shimabukuro

According to our database, Katsuhiko Shimabukuro authored at least 6 papers between 1992 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2022

QUBO Model Formulation Based on Petri Net Behavioral Description for Combinatorial Optimization Problems.

Keisuke Tokuhira, Morikazu Nakamura, Mitsunaga Kinjo, Katsuhiko Shimabukuro

ICO, 2022

2017

Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic.

Katsuhiko Shimabukuro, Michitaka Kameyama

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

2011

Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution.

Mitsunaga Kinjo, Katsuhiko Shimabukuro

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

2001

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.

Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

1998

Reconfigurable Current-Mode Multiple-Valued Residue Arithmetic Circuits.

Katsuhiko Shimabukuro, Chotei Zukeran

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1992

Design of a Multiple-Valued VLSI Processor for Digital Control.

Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992