Takahiro Hanyu

According to our database, Takahiro Hanyu authored at least 227 papers between 1987 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing.

Naoya Onizawa, Kota Katsuki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Neural Networks Learn. Syst., December, 2023

Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing.

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023

Local Energy Distribution Based Hyperparameter Determination for Stochastic Simulated Annealing.

Naoya Onizawa, Kyo Kuroki, Duckgyu Shin, Takahiro Hanyu

CoRR, 2023

Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems.

Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu

CoRR, 2023

Self-Adaptive Gate Control for Efficient Escape From Local Minimum Energy on Invertible Logic.

Naoya Onizawa, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 2023

Design of an Error-Tolerant Nonvolatile Register for Energy-Aware Intermittent Computing.

Kaede Sakai, Masanori Natsui, Takahiro Hanyu

Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023

Write-Energy Relaxation of MTJ-Based Quantized Neural-Network Hardware.

Ken Asano, Masanori Natsui, Takahiro Hanyu

Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023

High-Performance/Low-Area Power-Gating Switch Linear Array for Energy-Efficient LSIs with an Optimum Switch-Timing Control.

Fangcen Zhong, Masanori Natsui, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Improving Stochastic Quantum-Like Annealing Based on Rerandomization.

Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network.

Ken Asano, Masanori Natsui, Takahiro Hanyu

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

Stochastic Implementation of Simulated Quantum Annealing on PYNQ.

Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the International Conference on Field Programmable Technology, 2023

2022

Implementation of CMOS Invertible Logic on Zynq-SoC Platform: A Case Study of Training BNN.

Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

FLAP, 2022

Energy-Efficient Nonvolatile RISC-V CPU with a Custom Instruction-Controlled Accelerator.

Keisuke Sakamoto, Masanori Natsui, Takahiro Hanyu

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

A Spintronics-Based Nonvolatile FPGA and Its Application to Edge-AI Accelerator.

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Fast Solving Complete 2000-Node Optimization Using Stochastic-Computing Simulated Annealing.

Kota Katsuki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021

Multi-Context TCAM-Based Selective Computing: Design Space Exploration for a Low-Power NN.

Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A Design Framework for Invertible Logic.

Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

IEEE Open J. Circuits Syst., 2021

Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE J. Solid State Circuits, 2021

Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design Flow.

Daisuke Suzuki, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2021

Sparse Random Signals for Fast Convergence on Invertible Logic.

Naoya Onizawa, Makoto Kato, Hitoshi Yamagata, Koji Yano, Seiichi Shin, Hiroyuki Fujita, Takahiro Hanyu

IEEE Access, 2021

Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.

Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once- Write Shifting.

Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians.

Naoya Onizawa, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.

Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2020

Memristive Computational Memory Using Memristor Overwrite Logic (MOL).

Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2020

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.

Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Fast Hardware-based Learning Algorithm for Binarized Perceptrons using CMOS Invertible Logic.

Naoya Onizawa, Duckgyu Shin, Takahiro Hanyu

FLAP, 2020

Design of an MTJ-based Nonvolatile Multi-context Ternary Content-addressable Memory.

Naoya Onizawa, Ren Arakawa, Takahiro Hanyu

FLAP, 2020

Design Automation of Invertible Logic Circuit from a Standard HDL Description.

Makoto Kato, Naoya Onizawa, Takahiro Hanyu

FLAP, 2020

Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic.

Duckgyu Shin, Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

IEEE Access, 2020

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.

Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

Design and Evaluation of a Synthesizable Standard-Cell-Based Nonvolatile FPGA.

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

2019

Efficient CMOS Invertible Logic Using Stochastic Computing.

Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices.

Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu

Microelectron. J., 2019

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

IEEE J. Solid State Circuits, 2019

An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.

Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Design of a Current-Mode Linear-Sum-Based Bitcounting Circuit with an MTJ-Based Compensator for Binarized Neural Networks.

Tomoki Chiba, Masanori Natsui, Takahiro Hanyu

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

FPGA Implementation of Binarized Perceptron Learning Hardware Using CMOS Invertible Logic.

Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Multi-Context TCAM Based Selective Computing Architecture for a Low-Power NN.

Ren Arakawa, Naoya Onizawa, Jean-Philippe Diguet, Takahiro Hanyu

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018

A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception.

Kaushik Boga, François Leduc-Primeau, Naoya Onizawa, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

J. Signal Process. Syst., 2018

Networked Power-Gated MRAMs for Memory-Based Computing.

Jean-Philippe Diguet, Naoya Onizawa, Mostafa Rizk, Martha Johanna Sepúlveda, Amer Baghdadi, Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2018

MTJ-based asynchronous circuits for Re-initialization free computing against power failures.

Naoya Onizawa, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

Microelectron. J., 2018

Design of MTJ-Based nonvolatile logic gates for quantized neural networks.

Masanori Natsui, Tomoki Chiba, Takahiro Hanyu

Microelectron. J., 2018

An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling.

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Systematic Intrusion Detection Technique for an In-vehicle Network Based on Time-Series Feature Extraction.

Hiroki Suda, Masanori Natsui, Takahiro Hanyu

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

Design of a Low-Power MTJ-Based True Random Number Generator Using a Multi-voltage/Current Converter.

Shogo Mukaida, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

High-Precision Stochastic State-Space Digital Filters Based on Minimum Roundoff Noise Structure.

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Study of Stochastic Invertible Multiplier Designs.

Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only).

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

Area/Energy-Efficient Gammatone Filters Based on Stochastic Computation.

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

IEEE Trans. Very Large Scale Integr. Syst., 2017

VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing.

Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

IEEE Trans. Very Large Scale Integr. Syst., 2017

Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

IEEE Trans. Emerg. Top. Comput., 2017

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme.

Daisuke Suzuki, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2017

High-Accuracy and Area-Efficient Stochastic FIR Digital Filters Based on Hybrid Computation.

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

IEICE Trans. Inf. Syst., 2017

Foreword.

Takahiro Hanyu

IEICE Trans. Inf. Syst., 2017

NoC-MRAM architecture for memory-based computing: Database-search case study.

Mostafa Rizk, Jean-Philippe Diguet, Naoya Onizawa, Amer Baghdadi, Martha Johanna Sepúlveda, Y. Akgul, Vincent Gripon, Takahiro Hanyu

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Evaluation of Stochastic Cascaded IIR Filters.

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

Design of stochastic asymmetric compensation filters for auditory signal processing.

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masayuki Kawamata, Takahiro Hanyu

Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017

Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability.

Naoya Onizawa, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

Three-terminal MTJ-based nonvolatile logic circuits with self-terminated writing mechanism for ultra-low-power VLSI processor.

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Masanori Natsui

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing.

Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno

Proc. IEEE, 2016

Evaluation of Soft-Delay-Error Effects in Content-Addressable Memory.

Naoya Onizawa, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

J. Multiple Valued Log. Soft Comput., 2016

Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks.

Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.

Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations.

Naoya Onizawa, Takahiro Hanyu

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A study of a top-down error correction technique using Recurrent-Neural-Network-based learning.

Masanori Natsui, Naoto Sugaya, Takahiro Hanyu

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

VLSI implementation of deep neural networks using integral stochastic computing.

Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016

Context-Based Error Correction Scheme Using Recurrent Neural Network for Resilient and Efficient Intra-Chip Data Transmission.

Naoto Sugaya, Masanori Natsui, Takahiro Hanyu

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Realization of FIR Digital Filters Based on Stochastic/Binary Hybrid Computation.

Shunsuke Koshita, Naoya Onizawa, Masahide Abe, Takahiro Hanyu, Masayuki Kawamata

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.

Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Gammatone filter based on stochastic computation.

Naoya Onizawa, Shunsuke Koshita, Shuichi Sakamoto, Masahide Abe, Masayuki Kawamata, Takahiro Hanyu

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Gabor Filter Based on Stochastic Computation.

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

IEEE Signal Process. Lett., 2015

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEEE J. Solid State Circuits, 2015

Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2015

Stochastic implementation of the disparity energy model for depth perception.

Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya, Takahiro Hanyu, Warren J. Gross

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

Design of an STT-MTJ based true random number generator using digitally controlled probability-locked loop.

Satoshi Oosawa, Takayuki Konishi, Naoya Onizawa, Takahiro Hanyu

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.

Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure.

Daisuke Suzuki, Takahiro Hanyu

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Scaled IIR filter based on stochastic computation.

Naoya Onizawa, Shunsuke Koshita, Takahiro Hanyu

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Early-Stage Operation-Skipping Scheme for Low-Power Stochastic Image Processors.

Daisaku Katagiri, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Write-Operation Frequency Reduction for Nonvoratile Logic LSI with a Short Break-Even Time.

Takeaki Akutsu, Masanori Natsui, Takahiro Hanyu

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Design of a computational nonvolatile RAM for a greedy energy-efficient VLSI processor.

Akira Mochizuki, Naoto Yube, Takahiro Hanyu

Proceedings of the IECON 2015, 2015

Frequency-flexible stochastic Gabor filter.

Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya, Warren J. Gross, Takahiro Hanyu

Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.

Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

J. Signal Process. Syst., 2014

High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router.

Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

IEEE Trans. Computers, 2014

High-Throughput Partially Parallel Inter-Chip Link Architecture for Asynchronous Multi-Chip NoCs.

Naoya Onizawa, Akira Mochizuki, Hirokatsu Shirahama, Masashi Imai, Tomohiro Yoneda, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

IEICE Trans. Inf. Syst., 2014

Design of an Energy-Efficient Ternary Current-Mode Intra-Chip Communication Link for an Asynchronous Network-on-Chip.

Akira Mochizuki, Hirokatsu Shirahama, Yuma Watanabe, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2014

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure.

Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Soft-error tolerant transistor/magnetic-tunnel-junction hybrid non-volatile C-element.

Naoya Onizawa, Takahiro Hanyu

IEICE Electron. Express, 2014

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme.

Shoun Matsunaga, Akira Mochizuki, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

Design of an energy-efficient 2T-2MTJ nonvolatile TCAM based on a parallel-serial-combined search scheme.

Shoun Matsunaga, Akira Mochizuki, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2014

A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories.

Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross

Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Design of a soft-error tolerant 9-transistor/6-magnetic-tunnel-junction hybrid cell based nonvolatile TCAM.

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Fabrication of a MTJ-based multilevel resistor towards process-variaton-resilient logic LSI.

Masanori Natsui, Takahiro Hanyu

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Analog-to-stochastic converter using magnetic-tunnel junction devices.

Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications.

Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Soft-Delay-Error Evaluation in Content-Addressable Memory.

Naoya Onizawa, Shoun Matsunaga, Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Variation-Effect Analysis of MTJ-Based Multiple-Valued Programmable Resistors.

Masanori Natsui, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Design of a Quaternary Single-Ended Current-Mode Circuit for an Energy-Efficient Inter-chip Asynchronous Communication Link.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Associative Memories Based on Multiple-Valued Sparse Clustered Networks.

Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross

Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014

Energy-aware current-mode inter-chip link for a dependable GALS NoC platform.

Hirokatsu Shirahama, Akira Mochizuki, Yuma Watanabe, Takahiro Hanyu

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing.

Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo Kinoshita, Takahiro Hanyu, Tetsuo Endoh, Naoki Kasai, Hideo Ohno, Tadahiko Sugibayashi

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure.

Naoya Onizawa, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 20th IEEE International Symposium on Asynchronous Circuits and Systems, 2014

An NoC-based evaluation platform for safety-critical automotive applications.

Tomohiro Yoneda, Masashi Imai, Hiroshi Saito, Takahiro Hanyu, Kenji Kise, Yuichi Nakamura

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Highly reliable single-ended current-mode circuit for an inter-chip asynchronous communication link.

Akira Mochizuki, Hirokatsu Shirahama, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Design of Process-Variation-Resilient Analog Basic Components Using Magnetic-Tunnel-Junction Devices.

Masanori Natsui, Takahiro Hanyu

J. Multiple Valued Log. Soft Comput., 2013

Open-Fault Resilient Multiple-Valued Codes for Reliable Asynchronous Global Communication Links.

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2013

Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications.

Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Hideo Sato, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

IEICE Electron. Express, 2013

High-throughput CAM based on a synchronous overlapped search scheme.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Warren J. Gross, Takahiro Hanyu

IEICE Electron. Express, 2013

Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Design and Evaluation of a Differential Switching Gate for Low-Voltage Applications.

Masanori Natsui, Kiyohiro Kashiuchi, Takahiro Hanyu

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

Accurate and High-Speed Asynchronous Network-on-Chip Simulation Using Physical Wire-Delay Information.

Takahiro Hanyu, Yuma Watanabe, Atsushi Matsumoto

Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013

MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI.

Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor.

Takahiro Hanyu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu

Proceedings of the 19th IEEE International Symposium on Asynchronous Circuits and Systems, 2013

2012

Low-Energy Pipelined Multiple-Valued Current-Mode Circuit Based on Current-Level Control Technique.

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu

J. Multiple Valued Log. Soft Comput., 2012

Long-Range Asynchronous On-Chip Link Based on Multiple-Valued Single-Track Signaling.

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times.

Takashi Ohsawa, Hiroki Koike, Sadahiko Miura, Hiroaki Honjo, Keiichi Tokutome, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the Symposium on VLSI Circuits, 2012

A 3.14 um² 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture.

Shoun Matsunaga, Sadahiko Miura, Hiroaki Honjou, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Symposium on VLSI Circuits, 2012

Clockless Stochastic Decoding of Low-Density Parity-Check Codes.

Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet

Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Multi-chip NoCs for Automotive Applications.

Tomohiro Yoneda, Masashi Imai, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012

Fine-grained power-gating scheme of a nonvolatile logic-in-memory circuit for low-power motion-vector extraction.

Magdalena Sihotang, Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system.

Masanori Natsui, Takahiro Hanyu

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Area-efficient LUT circuit design based on asymmetry of MTJ's current switching for a nonvolatile FPGA.

Daisuke Suzuki, Masanori Natsui, Takahiro Hanyu

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs.

Luca Montesi, Zeljko Zilic, Takahiro Hanyu, Daisuke Suzuki

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes.

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu, Warren J. Gross

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Process-Variation-Resilient OTA Using MTJ-based Multi-level Resistance Control.

Masanori Natsui, Takaaki Nagashima, Takahiro Hanyu

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Quaternary 1T-2MTJ Cell Circuit for a High-Density and a High-Throughput Nonvolatile Bit-Serial CAM.

Shoun Matsunaga, Takahiro Hanyu

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

Systematic Coding Schemes for Low-Power Multiple-Valued Current-Mode Asynchronous Communication Links.

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

High-speed simulator including accurate MTJ models for spintronics integrated circuit design.

Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Hiroaki Honjo, Tadahiko Sugibayashi, Hiroki Koike, Takashi Ohsawa, Shunsuke Fukami, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Variation-resilient current-mode logic circuit design using MTJ devices.

Youngkeun Kim, Masanori Natsui, Takahiro Hanyu

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism.

Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet, Takahiro Hanyu

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

Implementation of a perpendicular MTJ-based read-disturb-tolerant 2T-2R nonvolatile TCAM based on a reversed current reading scheme.

Shoun Matsunaga, Masanori Natsui, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Low-Energy Asynchronous Interleaver for Clockless Fully Parallel LDPC Decoding.

Naoya Onizawa, Vincent C. Gaudet, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Design of an 8-nsec 72-bit-Parallel-Search Content-Addressable Memory Using a Phase-Change Device.

Satoru Hanzawa, Takahiro Hanyu

IEICE Trans. Electron., 2011

Design of a Low-Energy Nonvolatile Fully-Parallel Ternary CAM Using a Two-Level Segmented Match-Line Scheme.

Shoun Matsunaga, Akira Katsumata, Masanori Natsui, Takahiro Hanyu

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Complementary Multiple-Valued Encoding Scheme for Interconnect-Fault-Resilient Bidirectional Asynchronous Links.

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011

Adjacent-State monitoring based fine-grained power-gating scheme for a low-power asynchronous pipelined system.

Takao Kawano, Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Instant power-on nonvolatile FPGA based on MTJ/MOS-hybrid circuitry.

Takahiro Hanyu

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Interconnect-fault-resilient delay-insensitive asynchronous communication link based on current-flow monitoring.

Naoya Onizawa, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of the Design, Automation and Test in Europe, 2011

2010

Design of High-Throughput Fully Parallel LDPC Decoders Based on Wire Partitioning.

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

IEEE Trans. Very Large Scale Integr. Syst., 2010

Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme.

Hirokatsu Shirahama, Takashi Matsuura, Masanori Natsui, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2010

Highly Reliable Multiple-Valued One-Phase Signalling for an Asynchronous On-Chip Communication Link.

Naoya Onizawa, Takahiro Hanyu

IEICE Trans. Inf. Syst., 2010

Transient Characteristic of Fabricated Magnetic Tunnel Junction (MTJ) Programmed with CMOS Circuit.

Masashi Kamiyanagi, Fumitaka Iga, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

IEICE Trans. Electron., 2010

Study of the DC Performance of Fabricated Magnetic Tunnel Junction Integrated on Back-End Metal Line of CMOS Circuits.

Fumitaka Iga, Masashi Kamiyanagi, Shoji Ikeda, Katsuya Miura, Jun Hayakawa, Haruhiro Hasegawa, Takahiro Hanyu, Hideo Ohno, Tetsuo Endoh

IEICE Trans. Electron., 2010

Special session 8B: New topic MOS/MTJ-hybrid circuit with nonvolatile logic-in-memory architecture and its impact.

Takahiro Hanyu

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.

Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Low-Energy Pipelined Multiple-Valued Current-Mode Circuit with 8-Level Static Current-Source Control.

Masanori Natsui, Takashi Arimitsu, Takahiro Hanyu

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

One-Color Two-Phase Asynchronous Communication Links Based on Multiple-Valued Simultaneous Control.

Atsushi Matsumoto, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010

High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip.

Naoya Onizawa, Takahiro Hanyu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving.

Naoya Onizawa, Takahiro Hanyu, Vincent C. Gaudet

IEICE Trans. Electron., 2009

Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control.

Naoya Onizawa, Takahiro Hanyu

Proceedings of the ISMVL 2009, 2009

Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System.

Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui, Takahiro Hanyu

Proceedings of the ISMVL 2009, 2009

High-performance Asynchronous Intra-chip Communication Link based on a Multiple-valued Current-mode Single-track Scheme.

Yo Ohtake, Naoya Onizawa, Takahiro Hanyu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues.

Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Power-Aware Asynchronous Peer-to-Peer Duplex Communication System Based on Multiple-Valued One-Phase Signaling.

Kazuyasu Mizusawa, Naoya Onizawa, Takahiro Hanyu

IEICE Trans. Electron., 2008

Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation.

Masatomo Miura, Takahiro Hanyu

IEICE Trans. Electron., 2008

Design of High-Performance Quaternary Adders Based on Output-Generator Sharing.

Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.

Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.

Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu

Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008

2007

Design and Evaluation of a 54 x 54-bit Multiplier Based on Differential-Pair Circuitry.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2007

Asynchronous Peer-to-Peer Simplex/Duplex-Compatible Communication System Using a One-Phase Signaling Scheme.

Tomohiro Takahashi, Kazuyasu Mizusawa, Takahiro Hanyu

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor.

Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

High-Performance Multiple-Valued Comparator Based on Active-Load Dual-Rail Differential Logic for Crosstalk-Noise Reduction.

Akira Mochizuki, Masatomo Miura, Takahiro Hanyu

Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic.

Shoun Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, Takashi Nakamura, Hidemi Takasu

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-Valued Current-Signal Multiplexing.

Tomohiro Takahashi, Takahiro Hanyu

IEICE Trans. Electron., 2006

Design and Evaluation of a NULL-Convention Circuit Based on Dual-Rail Current-Mode Differential Logic.

Naoya Onizawa, Takahiro Hanyu

IEICE Trans. Electron., 2006

Design of a Low-Power Quaternary Flip-Flop Based on Dynamic Differential Logic.

Akira Mochizuki, Hirokatsu Shirahama, Takahiro Hanyu

IEICE Trans. Electron., 2006

Special Section on Novel Device Architectures and System Integration Technologies.

Takahiro Hanyu

IEICE Trans. Electron., 2006

Design of a Microprocessor Datapath Using Four-Valued Differential-Pair Circuits.

Akira Mochizuki, Takeshi Kitamura, Hirokatsu Shirahama, Takahiro Hanyu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

Highly reliable Multiple-Valued Circuit Based on Dual-Rail Differential Logic.

Akira Mochizuki, Takahiro Hanyu

Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006

2005

Control Signal Multiplexing Based Asynchronous Data Transfer Scheme Using Multiple-Valued Bidirectional Current-Mode Circuits.

Tomohiro Takahashi, Takahiro Hanyu

J. Multiple Valued Log. Soft Comput., 2005

Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.

Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2005

Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.

Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki

J. Multiple Valued Log. Soft Comput., 2005

Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.

Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2005

TMR-Based Logic-in-Memory Circuit for Low-Power VLSI.

Akira Mochizuki, Hiromitsu Kimura, Mitsuru Ibuki, Takahiro Hanyu

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Multiple-Valued Duplex Asynchronous Data Transfer Scheme for Interleaving in LDPC Decoders.

Naoya Onizawa, Akira Mochizuki, Takahiro Hanyu

Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

2004

Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI.

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu

IEEE J. Solid State Circuits, 2004

Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication.

Tomohiro Takahashi, Takahiro Hanyu

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding.

Akira Mochizuki, Takashi Takeuchi, Takahiro Hanyu

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices.

Hiromitsu Kimura, Kostas Pagiamtzis, Ali Sheikholeslami, Takahiro Hanyu

Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004

2003

Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications.

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2003

Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama

J. Multiple Valued Log. Soft Comput., 2003

Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.

Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

Multiple-Valued Dynamic Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003

2002

Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.

Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Fully Source-Coupled Logic Based Multiple-Valued VLSI.

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001

Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources.

Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.

Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

Challenge of a Multiple-Valued Technology in Recent Deep-Submicron VLSI.

Takahiro Hanyu

Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001

2000

Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama

Proceedings of the 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 2000

Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.

Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama

Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000

1999

Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.

Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama

Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999

1998

Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.

Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama

Syst. Comput. Jpn., 1998

Design and evaluation of a digit-parallel multiple-valued content-addressable memory.

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Syst. Comput. Jpn., 1998

Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.

Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.

Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama

Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998

1997

One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.

Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama

Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997

Low-power multiple-valued current-mode integrated circuit with current-source control and its application.

Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

Design of a one-transistor-cell multiple-valued CAM.

Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama

IEEE J. Solid State Circuits, 1996

Design of a one-transistor-cell multiple-valued CAM.

Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama

IEEE J. Solid State Circuits, 1996

A Multiple-Valued Ferroelectric Content-Addressable Memory.

Ali Sheikholeslami, P. Glenn Gulak, Takahiro Hanyu

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Quaternary Universal-Literal CAM for Cellular Logic Image Processing.

Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama

Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

1995

A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic.

Takahiro Hanyu, Michitaka Kameyama

IEEE J. Solid State Circuits, November, 1995

Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate.

Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama

IEICE Trans. Inf. Syst., 1995

Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.

Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1994

Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.

Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

1993

A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions.

Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi

Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993

1992

Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems.

Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems.

Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

A Floating-Gate-MOS-Based Multiple-Valued Associative Memory.

Takahiro Hanyu, Tatsuo Higuchi

Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991

1990

Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices.

Takahiro Hanyu, Tatsuo Higuchi

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1989

Design of a Multiple-Valued Associative Memory.

Takahiro Hanyu, Tatsuo Higuchi

Syst. Comput. Jpn., 1989

1987

Design and implementation of an nmos image processor based on quaternary logic.

Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi

Syst. Comput. Jpn., 1987