Kavita Khare

IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications.

[BibT_eX]

[DOI]

Aizaz Tirmizi

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error.

[BibT_eX]

[DOI]

Int. J. Circuit Theory Appl., 2022

2021

A Novel Approach for Optimal Design of Sample Rate Conversion Filter Using Linear Optimization Technique.

[BibT_eX]

[DOI]

Divya Gautam

Bhavana P. Shrivastava

IEEE Access, 2021

2019

Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology.

[BibT_eX]

[DOI]

Ajay Kumar Dadoria

Circuits Syst. Signal Process., 2019

2018

New Leakage Reduction Techniques for FinFET Technology with Its Application.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2018

2016

Concept, Design, and Implementation of Reconfigurable CORDIC.

[BibT_eX]

[DOI]

Pramod Kumar Meher

IEEE Trans. Very Large Scale Integr. Syst., 2016

Low-Power High Speed 1-bit Full Adder Circuit Design.

[BibT_eX]

[DOI]

Shailesh Dwivedi

Ajay Kumar Dadoria

ICTCS, 2016

Leakage Power Reduction Technique by using FinFET Technology.

[BibT_eX]

[DOI]

Ajay Kumar Dadoria

R. P. Singh

ICTCS, 2016

2013

Leading One Detection Hyperbolic CORDIC with Enhanced Range of Convergence.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2013

Scale-Free Hyperbolic CORDIC Processor and Its Application to Waveform Generation.

[BibT_eX]

[DOI]

Pramod Kumar Meher

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

CORDIC-based window implementation to minimise area and pipeline depth.

[BibT_eX]

[DOI]

IET Signal Process., 2013

Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits.

[BibT_eX]

[DOI]

Tarun Kumar Gupta

Circuits Syst. Signal Process., 2013

Efficient Window-Architecture Design Using Completely Scaling-Free CORDIC Pipeline.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

3D CORDIC Algorithm Based Cartesian to Spherical Coordinate Converter.

[BibT_eX]

[DOI]

Anita Jain

Proceedings of the VLSI Design and Test, 17th International Symposium, 2013

2012

FPGA Implementation of Cross Virtual Concatenation Transmitter/ Receiver for Data Transmission over Next Generation SDH Systems.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Area-Time Efficient Scaling-Free CORDIC Using Generalized Micro-Rotation Selection.

[BibT_eX]

[DOI]

Pramod Kumar Meher

IEEE Trans. Very Large Scale Integr. Syst., 2012

Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm.

[BibT_eX]

[DOI]

Comput. J., 2012

Hardware Efficient Architecture for Generating Sine/Cosine Waves.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

2011

VCAT synchroniser - reduction of buffer size in VCAT enabled next generation SDH networks.

[BibT_eX]

[DOI]

Eur. Trans. Telecommun., 2011

2010

Standby leakage reduction in nanoscale CMOS VLSI circuits.

[BibT_eX]

[DOI]

J. Deshmukh

Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

2009

Differential Delay Compensator -- A New Approach to Reduce Buffer Size in VCAT Enabled Next Generation SDH Networks.

[BibT_eX]

[DOI]

Proceedings of the ARTCom 2009, 2009

FPGA Design and Implementation Issues of Artificial Neural Network Based PID Controllers.

[BibT_eX]

[DOI]

Vikas Gupta

R. P. Singh

Proceedings of the ARTCom 2009, 2009

2008

100Mbps Ethernet data transmission over SDH networks using Cross Virtual Concatenation.

[BibT_eX]

[DOI]