Kavitha S
Orcid: 0000-0002-4772-6031Affiliations:
- Indian Institute of Information Technology, Design and Manufacturing, Kancheepuram (IIITDM Kancheepuram), Frontier Electronics Laboratory, India (PhD 2025)
According to our database1,
Kavitha S authored at least 7 papers
between 2021 and 2026.
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Bibliography
2026
In-Memory Computing Paradigm Using Energy-Efficient Analog Arithmetic for DNA Sequence Alignment.
IEEE Trans. Emerg. Top. Comput., 2026
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021