Bhupendra Singh Reniwal
Orcid: 0000-0002-5586-5365
According to our database1,
Bhupendra Singh Reniwal authored at least 22 papers
between 2013 and 2026.
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Bibliography
2026
In-Memory Computing Paradigm Using Energy-Efficient Analog Arithmetic for DNA Sequence Alignment.
IEEE Trans. Emerg. Top. Comput., 2026
NA-STM Enhanced Energy-Efficient Custom Spiking U-Net Denoiser for Noise-Robust CIFAR-10 Classification.
IEEE Open J. Comput. Soc., 2026
2025
Spatially Invariant Convolutional Spiking Neural Network For Resource-Constrained IoT Devices.
Circuits Syst. Signal Process., May, 2025
Highly Accurate and Energy Efficient Convolutional Spiking Neural Network for Traffic Sign Recognition.
IEEE Access, 2025
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Design and Analysis of Multibit Multiply and Accumulate (MAC) unit: An Analog In-Memory Computing Approach.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
2022
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array.
Proceedings of the VLSI Design and Test - 26th International Symposium, 2022
2021
Energy Efficient, Hamming Code Technique for Error Detection/Correction Using In-Memory Computation.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021
2019
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM.
Circuits Syst. Signal Process., 2019
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019
2018
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design.
Integr., 2018
2017
Design and investigation of variability aware sense amplifier for low power, high speed SRAM.
Microelectron. J., 2017
J. Low Power Electron., 2017
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
2016
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance.
Circuits Syst. Signal Process., 2016
2015
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small I<sub>cell</sub> SRAM Using FinFET.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2013
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM.
Proceedings of the VLSI Design and Test, 17th International Symposium, 2013