Binsu J. Kailath

According to our database, Binsu J. Kailath authored at least 26 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

ShiftMUX: Reconfigurable 4:1 MUX-Based In-Memory Shifter for Multiplication-Less Deep Neural Network Accelerations.

Vinodh Kumar Bose, Rajiv V. Joshi, Yu Cao, Binsu J. Kailath

IEEE J. Emerg. Sel. Topics Circuits Syst., June, 2026

In-Memory Computing Paradigm Using Energy-Efficient Analog Arithmetic for DNA Sequence Alignment.

Kavitha Soundrapandiyan, Bhupendra Singh Reniwal, Binsu J. Kailath

IEEE Trans. Emerg. Top. Comput., 2026

Spike-Based Time-Domain ECG Wave Delineation for Low-Power VLSI Implementation.

Priya K, Binsu J. Kailath

Proceedings of the 39th International Conference on VLSI Design & 25th International Conference on Embedded Systems, 2026

2025

SleepISI: A Neuromorphic Time-Domain EEG Classification Framework Using Inter-Spike Intervals From AdEx Encoding of C4-A1 Signals.

Asha V., Vasanthi R, Sapna E. Sreedharan, Kalpana Settu, Binsu J. Kailath

IEEE J. Biomed. Health Informatics, December, 2025

Atrial Flutter Detection System by AdEx Encoded Lead-II ECG.

Sushmi R, Priya K, Binsu J. Kailath

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

Hardware-Efficient Rwave Delineation by AdEx Encoded Lead II ECG: No Filters, No Preprocessing.

Priya K, Binsu J. Kailath

Proceedings of the 20th International Conference on PhD Research in Microelectronics and Electronics, 2025

Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory Computing.

B. Vinodh Kumar, Binsu J. Kailath

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

A Configurable RISC-V Vector Processor with FSM-Driven Accelerator for Data-Intensive Workloads.

Akkapolu Sankararao, Vashist Managari, Naveen Kollepara, Binsu J. Kailath

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

Fast and Energy-Efficient Pipelined Vedic Multiplier Design for Modern Cryptographic Processors.

Akkapolu Sankararao, Naveen Kollepara, Vashist Managari, Binsu J. Kailath

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2025

2024

Development of Accurate Model for Memristor-Based Filters and Oscillators: Amplitude, Frequency and Ramp-Rate Dependent Analysis.

Rami Reddy Sowmya, Arige Sumanth, Binsu J. Kailath, Tejendra Dixit

IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

SNN with Gradient-based Backpropagation algorithm for ECG arrhythmia classification with LIF neuron and AdEx neuron.

Bana Shanmuga Sai Badrinatha Reddy, Priya K, Binsu J. Kailath

Proceedings of the 28th International Symposium on VLSI Design and Test, 2024

CiMComp: An Energy Efficient Compute-in-Memory Based Comparator for Convolutional Neural Networks.

Kavitha S, Binsu J. Kailath, Bhupendra Singh Reniwal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2022

Graph-Based Circuit Simulator for Switched Capacitor Circuits.

Dinesh Ganesan, Binsu J. Kailath

IEEE Des. Test, 2022

2021

High speed Power efficient Vedic arithmetic modules on Zedboard-Zynq-7000 FPGA.

Sujitha S, Binsu J. Kailath

Int. J. Circuit Theory Appl., 2021

Tree/link method for transfer function and stability analysis of switched-capacitor circuits.

Dinesh Ganesan, Binsu J. Kailath

Int. J. Circuit Theory Appl., 2021

Bistable-Triplet STDP circuit without external memory for Integrating with Silicon Neurons.

Sathiya Jothi. S, Binsu J. Kailath

Proceedings of the IEEE World AI IoT Congress, 2021

A Novel Biphasic Neuron Encoder Implementation.

Madhuvanthi Srivatsav R, Binsu J. Kailath

Proceedings of the IEEE World AI IoT Congress, 2021

2020

Reusable Spiking Neural Network Architecture.

Sai G. Pavan, Binsu J. Kailath

Proceedings of the 11th IEEE Annual Ubiquitous Computing, 2020

A Silicon Neuron-based Bio-Front-End for Ultra Low Power Bio-Monitoring at the Edge.

T. P. Shivangi, M. Rahimi, Gaetano D. Gargiulo, Binsu J. Kailath, Tara Julia Hamilton

Proceedings of the 2020 IEEE Symposium Series on Computational Intelligence, 2020

2019

FPGA Implementation of Speech Recognizer for Isolated Words.

Nithya K, Muralidhar Gadamsetty, Binsu J. Kailath

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2019

2018

PLL architecture with a composite PFD and variable loop filter.

Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath

IET Circuits Devices Syst., 2018

2017

Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder.

K. Dheepika, K. S. Jevasankari, Vippin Chandhar, Binsu J. Kailath

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur.

Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath

IEICE Electron. Express, 2016

Switched-capacitor circuit simulator in Q-V domain including nonidealities.

G. Muralidhar, Dinesh Ganesan, Binsu J. Kailath

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Improved alias rejection using interleaved CIC decimation filter.

S. S. Karthikeyan, Dinesh Ganesan, Binsu J. Kailath

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

QSCsim - Charge Based Switched Capacitor Simulator.

Binsu J. Kailath, Dinesh Ganesan

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016