Keng-Jan Hsiao

According to our database, Keng-Jan Hsiao authored at least 9 papers between 2006 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A Load-Adaptive Class-G Headphone Amplifier With Supply-Rejection Bandwidth Enhancement Technique.

Shon-Hang Wen, Chien-Ming Chen, Cheng-Chung Yang, Chieh-Hung Chen, Jia-Feng Jiang, Keng-Jan Hsiao, Cheng-Yu Chien

IEEE J. Solid State Circuits, 2016

2015

A 130dB PSRR, 108dB DR and 95dB SNDR, ground-referenced audio decoder with PSRR-enhanced load-adaptive Class-G 16Ohm headphone amplifiers.

Shon-Hang Wen, Chien-Ming Chen, Cheng-Chung Yang, Chieh-Hung Chen, Jia-Feng Jiang, Keng-Jan Hsiao, Cheng-Yu Chien

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

17.7 A 1.89nW/0.15V self-charged XO for real-time clock generation.

Keng-Jan Hsiao

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2012

A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation.

Keng-Jan Hsiao

Proceedings of the Symposium on VLSI Circuits, 2012

2011

An injection-locked ring PLL with self-aligned injection window.

Che-Fu Liang, Keng-Jan Hsiao

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation.

Keng-Jan Hsiao, Tai-Cheng Lee

IEEE J. Solid State Circuits, 2009

2008

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning.

Keng-Jan Hsiao, Tai-Cheng Lee

IEEE J. Solid State Circuits, 2008

A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation.

Keng-Jan Hsiao, Tai-Cheng Lee

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2006

The design and analysis of a DLL-based frequency synthesizer for UWB application.

Tai-Cheng Lee, Keng-Jan Hsiao

IEEE J. Solid State Circuits, 2006