Che-Fu Liang

According to our database, Che-Fu Liang authored at least 15 papers between 2006 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

10.8 A wideband fractional-N ring PLL using a near-ground pre-distorted switched-capacitor loop filter.

Che-Fu Liang, Ping-Ying Wang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

A 1V fractional-N PLL with nonlinearity-insensitive modulator.

Yi-Chieh Huang, Che-Fu Liang, Ping-Ying Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

15.3 A 2.4GHz ADPLL with digital-regulated supply-noise-insensitive and temperature-self-compensated ring DCO.

Yi-Chieh Huang, Che-Fu Liang, Hsien-Sheng Huang, Ping-Ying Wang

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A wideband fractional-N ring PLL with fractional-spur suppression using spectrally shaped segmentation.

Tsung-Kai Kao, Che-Fu Liang, Hsien-Hsiang Chiu, Michael Ashburn

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2011

An injection-locked ring PLL with self-aligned injection window.

Che-Fu Liang, Keng-Jan Hsiao

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier.

Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2009

2008

10-Gb/s Inductorless CDRs With Digital Frequency Calibration.

Che-Fu Liang, Hong-Lin Chu, Shen-Iuan Liu

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2008

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems.

Che-Fu Liang, Shin-Hua Chen, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2008

A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells.

Che-Fu Liang, Shen-Iuan Liu

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Spur-Suppression Techniques for Frequency Synthesizers.

Che-Fu Liang, Hsin-Hua Chen, Shen-Iuan Liu

IEEE Trans. Circuits Syst. II Express Briefs, 2007

A Multi-Band Burst-Mode Clock and Data Recovery Circuit.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

IEICE Trans. Electron., 2007

2006

A Calibrated Pulse Generator for Impulse-Radio UWB Applications.

Che-Fu Liang, Shih-Tsai Liu, Shen-Iuan Liu

IEEE J. Solid State Circuits, 2006

A 14-band Frequency Synthesizer for MB-OFDM UWB Application.

Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS.

Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006