Kiichi Yamashita

According to our database1, Kiichi Yamashita authored at least 8 papers between 1976 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2010
17 Gb/s VCSEL driver using double-pulse asymmetric emphasis technique in 90-nm CMOS for optical interconnection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture.
IEEE J. Solid State Circuits, 2009

2008
Sandwich Structure Type RF-MEMS Variable Capacitor with Low Voltage Controllability and Wide Tuning Range.
IEICE Trans. Commun., 2008

Feedthrough reduction technique for track-and-hold circuit with body-bias control circuit.
IEICE Electron. Express, 2008

2007
A 1-GHz, 56.3-dB SFDR CMOS track-and-hold circuit with body-bias control circuit.
IEICE Electron. Express, 2007

2006
Design of Low-Noise, Low-Power 10-GHz VCO Using 0.18-µm CMOS Technology.
IEICE Trans. Electron., 2006

1984
Instantaneous In-Service Fault Location Scheme For Digital Transmission Systems.
Proceedings of the IEEE International Conference on Communications: Links for the Future, 1984

1976
Optical Pulse Formats for Fiber Optic Digital Communications.
IEEE Trans. Commun., 1976


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