Kirsten E. Moselund

Orcid: 0000-0003-4713-2046

According to our database1, Kirsten E. Moselund authored at least 14 papers between 2007 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Single-mode emission from a topological lattice with distributed gain and dielectric medium.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

2021
Butt-Coupled III-V Photodetector Monolithically Integrated on SOI with data reception at 50 Gbps OOK.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2021

2020
Coupled VO2 oscillators circuit as analog first layer filter in convolutional neural networks.
CoRR, 2020

Ultra-Thin III-V Photodetectors Epitaxially Integrated on Si with Bandwidth Exceeding 25 GHz.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

In-plane monolithic integration of scaled III-V photonic devices.
Proceedings of the European Conference on Optical Communications, 2020

2019
Monolithically integrated catalyst-free High Aspect Ratio InAs-On-Insulator (InAsOI) FinFETs for pH sensing.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

High-Performance InGaAs-on-Silicon Technology Platform For Logic and RF Applications.
Proceedings of the 2019 IEEE BiCMOS and Compound semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2019

2018
Resistive Coupled VO2 Oscillators for Image Recognition.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

Monolithic Integration of III -V on silicon for photonic and electronic applications.
Proceedings of the 76th Device Research Conference, 2018

2016
Complementary III-V heterostructure tunnel FETs.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

Ballistic transport and high thermopower in one-dimensional InAs nanowires.
Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014
III-V semiconductor nanowires for future devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2008
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007


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