Giovanni De Micheli

According to our database1, Giovanni De Micheli authored at least 518 papers between 1983 and 2018.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2001, "For his contributions to the design technologies of integrated circuits and systems and for his service to the community via a prominent textbook.".

IEEE Fellow

IEEE Fellow 1994, "For contribution to synthesis algorithms for the design of electronic circuits and systems.".

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2018
An IoT Solution for Online Monitoring of Anesthetics in Human Serum Based on an Integrated Fluidic Bioelectronic System.
IEEE Trans. Biomed. Circuits and Systems, 2018

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging.
IEEE Trans. Biomed. Circuits and Systems, 2018

Pairs of majority-decomposing functions.
Inf. Process. Lett., 2018

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice.
IEEE Design & Test, 2018

Exact Synthesis of ESOP Forms.
CoRR, 2018

The EPFL Logic Synthesis Libraries.
CoRR, 2018

Developing Synthesis Flows Without Human Knowledge.
CoRR, 2018

SAT-based {CNOT, T} Quantum Circuit Synthesis.
Proceedings of the Reversible Computation - 10th International Conference, 2018

Keynote Talk: NoCs: A Short History of Success and a Long Future.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

A Flexible Front-End for Wearable Electrochemical Sensing.
Proceedings of the 2018 IEEE International Symposium on Medical Measurements and Applications, 2018

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

End-to-End Industrial Study of Retiming.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Deep Learning for Logic Optimization Algorithms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Majority logic synthesis.
Proceedings of the International Conference on Computer-Aided Design, 2018

A novel electrochemical sensor for non-invasive monitoring of lithium levels in mood disorders.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Practical exact synthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards high-performance polarity-controllable FETs with 2D materials.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Developing synthesis flows without human knowledge.
Proceedings of the 55th Annual Design Automation Conference, 2018

SAT based exact synthesis using DAG topology families.
Proceedings of the 55th Annual Design Automation Conference, 2018

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Functional decomposition using majority.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.
IEEE Trans. Emerging Topics Comput., 2017

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.
IEEE Trans. on Circuits and Systems, 2017

Cyber-Medical Systems: Requirements, Components and Design Examples.
IEEE Trans. on Circuits and Systems, 2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.
IEEE Trans. Biomed. Circuits and Systems, 2017

A Differential Electrochemical Readout ASIC With Heterogeneous Integration of Bio-Nano Sensors for Amperometric Sensing.
IEEE Trans. Biomed. Circuits and Systems, 2017

Nano-Tera.ch: Information Technology for Health, Environment, and Energy.
IEEE Design & Test, 2017

Logic Synthesis for Quantum Computing.
CoRR, 2017

A PLiM Computer for the Internet of Things.
IEEE Computer, 2017

Networks on Chips: 15 Years Later.
IEEE Computer, 2017

Optimization opportunities in RRAM-based FPGA architectures.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Classifying Functions with Exact Synthesis.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

RM3 based logic synthesis (Special session paper).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient electronic measurement interface for memristive biosensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling exact delay synthesis.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Wave pipelining for majority-based beyond-CMOS technologies.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design automation and design space exploration for quantum computers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Busy man's synthesis: Combinational delay optimization with SAT.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Endurance management for resistive Logic-In-Memory computing architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Single-FPGA complete 3D and 2D medical ultrasound imager.
Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Hierarchical Reversible Logic Synthesis Using LUTs.
Proceedings of the 54th Annual Design Automation Conference, 2017

Live demonstration: An IoT smartwatch-based system for intensive care monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Live demonstration: Inexpensive 1024-channel 3D telesonography system on FPGA.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Inexpensive 1024-channel 3D telesonography system on FPGA.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Raspberry Pi driven flow-injection system for electrochemical continuous monitoring platforms.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A novel basis for logic rewriting.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Memristive Biosensors Integration With Microfluidic Platform.
IEEE Trans. on Circuits and Systems, 2016

A Study on the Programming Structures for RRAM-Based FPGA Architectures.
IEEE Trans. on Circuits and Systems, 2016

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2016

A Sound and Complete Axiomatization of Majority-n Logic.
IEEE Trans. Computers, 2016

A CMOS Amperometric System for Multi-Neurotransmitter Detection.
IEEE Trans. Biomed. Circuits and Systems, 2016

In-Vivo Validation of Fully Implantable Multi-Panel Devices for Remote Monitoring of Metabolism.
IEEE Trans. Biomed. Circuits and Systems, 2016

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs.
Microelectronics Journal, 2016

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.
Microelectronics Journal, 2016

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
JETC, 2016

Emerging Technology-Based Design of Primitives for Hardware Security.
JETC, 2016

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Design Automation and Design Space Exploration for Quantum Computers.
CoRR, 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

Enumeration of Reversible Functions and Its Application to Circuit Complexity.
Proceedings of the Reversible Computation - 8th International Conference, 2016

Inversion optimization in Majority-Inverter Graphs.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Paradigm-Shifting Players for IoT: Smart-Watches for Intensive Care Monitoring.
Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Notes on Majority Boolean Algebra.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Simultaneous monitoring of anesthetics and therapeutic compounds with a portable multichannel potentiostat.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An integrated platform for differential electrochemical and ISFET sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SAT-Based Combinational and Sequential Dependency Computation.
Proceedings of the Hardware and Software: Verification and Testing, 2016

Single-FPGA 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Fast hierarchical NPN classification.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Nano-fabricated memristive biosensors for biomedical applications with liquid and dried samples.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Optimizing Majority-Inverter Graphs with functional hashing.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Panel: Looking backwards and forwards.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Demo: Efficient delay and apodization for on-FPGA 3D ultrasound.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

An MIG-based compiler for programmable logic-in-memory architectures.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Majority-based synthesis for nanotechnologies.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory.
IEEE Trans. VLSI Syst., 2015

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.
IEEE Trans. VLSI Syst., 2015

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture.
IEEE Trans. VLSI Syst., 2015

New Logic Synthesis as Nanotechnology Enabler.
Proceedings of the IEEE, 2015

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems.
JETC, 2015

FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise.
CoRR, 2015

A Sound and Complete Axiomatization of Majority-n Logic.
CoRR, 2015

NEM relay design with biconditional binary decision diagrams.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A study on buffer distribution for RRAM-based FPGA routing structures.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A fast pruning technique for low-power inexact Circuit design.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploiting Circuit Duality to Speed up SAT.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Full system for translational studies of personalized medicine with free-moving mice.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A neural approach to drugs monitoring for personalized medicine.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

FPGA-SPICE: A simulation-based power estimation framework for FPGAs.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accurate power analysis for near-Vt RRAM-based FPGA.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A surface potential and current model for polarity-controllable silicon nanowire FETs.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Fault modeling in controllable polarity silicon nanowire circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Tackling the bottleneck of delay tables in 3D ultrasound imaging.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A ultra-low-power FPGA based on monolithically integrated RRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

The future of electronics, semiconductors, and design in Europe: panel.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Wireless monitoring in intensive care units by a 3D-printed system with embedded electronic.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Multiple Independent Gate FETs: How many gates do we need?
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.
IEEE Trans. on Circuits and Systems, 2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. on Circuits and Systems, 2014

An Integrated Control and Readout Circuit for Implantable Multi-Target Electrochemical Biosensing.
IEEE Trans. Biomed. Circuits and Systems, 2014

Full Fabrication and Packaging of an Implantable Multi-Panel Device for Monitoring of Metabolites in Small Animals.
IEEE Trans. Biomed. Circuits and Systems, 2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.
JETC, 2014

Representation of Medical Guidelines with a Computer Interpretable Model.
International Journal on Artificial Intelligence Tools, 2014

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Novel configurable logic block architecture exploiting controllable-polarity transistors.
Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Parallel vs. serial inter-plane communication using TSVs.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Memristor-based devices for sensing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Quantitative estimation of biological cell surface receptors by segmenting conventional fluorescence microscopy images.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

3D serial TSV link for low-power chip-to-chip communication.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

A high-performance low-power near-Vt RRAM-based FPGA.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Pattern-based FPGA logic block and clustering algorithm.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A new basic logic structure for data-path computation (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Electrochemical biochip for applications to wireless and batteryless monitoring of free-moving mice.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Majority Logic Synthesis for Spin Wave Technology.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Advanced system on a chip design based on controllable-polarity FETs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient manipulation package for Biconditional Binary Decision Diagrams.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Novel readout circuit for memristive biosensors in cancer detection.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Glucose and lactate monitoring in cell cultures with a wireless android interface.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Programmable active pixel sensor for low-light biomedical applications.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

A lightweight cryptographic system for implantable biosensors.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Sub-mW reconfigurable interface IC for electrochemical sensing.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: A smart camera for real-time monitoring of fluorescent cell biomarkers.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: In-situ biosensors array for cell culture monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

Data compression via logic synthesis.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.
IEEE Trans. VLSI Syst., 2013

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs.
IEEE Trans. Industrial Informatics, 2013

Designing best effort networks-on-chip to meet hard latency constraints.
ACM Trans. Embedded Comput. Syst., 2013

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.
IEEE Trans. on Circuits and Systems, 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.
IEEE Trans. Computers, 2013

A Study of Multi-Layer Spiral Inductors for Remote Powering of Implantable Sensors.
IEEE Trans. Biomed. Circuits and Systems, 2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores.
Parallel Computing, 2013

An Enhanced Design Methodology for Resonant Clock Trees.
J. Low Power Electronics, 2013

Cell transformations and physical design techniques for 3D monolithic integrated circuits.
JETC, 2013

A combined sensor placement and convex optimization approach for thermal management in 3D-MPSoC with liquid cooling.
Integration, 2013

A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Efficient arithmetic logic gates using double-gate silicon nanowire FETs.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.
Proceedings of the 14th Latin American Test Workshop, 2013

Runtime 3-D stacked cache management for chip-multiprocessors.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

3.5-D integration: A case study.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Parameterized SVM for personalized drug concentration prediction.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

A configurable IC to contol, readout, and calibrate an array of biosensors.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Electronic implants: power delivery and management.
Proceedings of the Design, Automation and Test in Europe, 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013

Panel: "will 3D-IC remain a technology of the future... even in the future?".
Proceedings of the Design, Automation and Test in Europe, 2013

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Online thermal control methods for multiprocessor systems.
ACM Trans. Design Autom. Electr. Syst., 2012

New Approaches for Carbon Nanotubes-Based Biosensors and Their Application to Cell Culture Monitoring.
IEEE Trans. Biomed. Circuits and Systems, 2012

Fully Integrated Biochip Platforms for Advanced Healthcare.
Sensors, 2012

Electrochemical Detection of Anti-Breast-Cancer Agents in Human Serum by Cytochrome P450-Coated Carbon Nanotubes.
Sensors, 2012

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.
Proceedings of the IEEE, 2012

Inter-Plane Communication Methods for 3-D ICs.
J. Low Power Electronics, 2012

Effect of process variations in 3D global clock distribution networks.
JETC, 2012

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.
J. Electrical and Computer Engineering, 2012

Editorial.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

GMS: Generic memristive structure for non-volatile FPGAs.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

The combined effect of process variations and power supply noise on clock skew and jitter.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhanced wafer matching heuristics for 3-D ICs.
Proceedings of the 17th IEEE European Test Symposium, 2012

TAT-based formal representation of medical guidelines: Imatinib case-study.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Voltage propagation method for 3-D power grid analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Integrated biosensors for personalized medicine.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A distributed interleaving scheme for efficient access to WideIO DRAM memory.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A Drug Administration Decision Support System.
Proceedings of the 2012 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2012

Medical guidelines reconciling medical software and electronic devices: Imatinib case-study.
Proceedings of the 12th IEEE International Conference on Bioinformatics & Bioengineering, 2012

Engineering complex systems for health, security and the environment.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
An Efficient Gate Library for Ambipolar CNTFET Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs.
Proceedings of the Industrial Embedded Systems (SIES), 2011

Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A DRAM Centric NoC Architecture and Topology Design Approach.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Simulation Based Buffer Sizing Algorithm for Network on Chips.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

pH sensing with temperature compensation in a Molecular Biosensor for drugs detection.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Skew variability in 3-D ICs with multiple clock domains.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Alternative design methodologies for the next generation logic switch.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Example-based support vector machine for drug concentration analysis.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Analytical heat transfer model for thermal through-silicon vias.
Proceedings of the Design, Automation and Test in Europe, 2011

An integrated platform for advanced diagnostics.
Proceedings of the Design, Automation and Test in Europe, 2011

Logic synthesis and physical design: Quo vadis?
Proceedings of the Design, Automation and Test in Europe, 2011

Personalized modeling for drug concentration prediction using Support Vector Machine.
Proceedings of the 4th International Conference on Biomedical Engineering and Informatics, 2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.
Proceedings of the Low Power Networks-on-Chip., 2011

2010
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.
IEEE Trans. on Circuits and Systems, 2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Capacitance DNA bio-chips improved by new probe immobilization strategies.
Microelectronics Journal, 2010

Process-induced skew variation for scaled 2-D and 3-D ICs.
Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Multicore thermal management using approximate explicit model predictive control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Temperature sensor placement in thermal management systems for MPSoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Memristive devices fabricated with silicon nanowire schottky barrier transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Characterization of memristive Poly-Si Nanowires via empirical physical modelling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Physical design tradeoffs in power distribution networks for 3-D ICs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Synthesis of regular computational fabrics with ambipolar CNTFET technology.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Online convex optimization-based algorithm for thermal management of MPSoCs.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.
Proceedings of the Design, Automation and Test in Europe, 2010

Power consumption of logic circuits in ambipolar carbon nanotube technology.
Proceedings of the Design, Automation and Test in Europe, 2010

Panel: First commandment at least, do nothing well!
Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.
Proceedings of the 47th Design Automation Conference, 2010

Networks on Chips: from research to products.
Proceedings of the 47th Design Automation Conference, 2010

Exploring programming model-driven QoS support for NoC-based platforms.
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Methods for Designing Reliable Probe Arrays.
Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

Design of networks on chips for 3D ICs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Synchronization and power integrity issues in 3-D ICs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Performance analysis of 3-D monolithic integrated circuits.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
Processor Speed Control With Thermal Constraints.
IEEE Trans. on Circuits and Systems, 2009

Thermal Balancing Policy for Multiprocessor Stream Computing Platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

An Outlook on Design Technologies for Future Integrated Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2009

Modeling stochasticity and robustness in gene regulatory networks.
Bioinformatics, 2009

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

A method for calculating hard QoS guarantees for Networks-on-Chip.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation.
Proceedings of IEEE International Conference on Communications, 2009

Power distribution paths in 3-D ICS.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.
Proceedings of the Design, Automation and Test in Europe, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.
Proceedings of the Design, Automation and Test in Europe, 2009

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009

Panel session - Consolidation, a modern "Moor of Venice" tale.
Proceedings of the Design, Automation and Test in Europe, 2009

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009

NoC topology synthesis for supporting shutdown of voltage islands in SoCs.
Proceedings of the 46th Design Automation Conference, 2009

Decoding nanowire arrays fabricated with the multi-spacer patterning technique.
Proceedings of the 46th Design Automation Conference, 2009

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.
Proceedings of the 2009 International Conference on Compilers, 2009

Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform.
Proceedings of the BIODEVICES 2009, 2009

A control theory approach for thermal balancing of MPSoC.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Synthesis of networks on chips for 3D systems on chips.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integration, 2008

Network-on-Chip design and synthesis outlook.
Integration, 2008

On-chip implementation of multiprocessor networks and switch fabrics.
IJES, 2008

Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow.
IEEE Design & Test of Computers, 2008

Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.
Computers & Mathematics with Applications, 2008

Synchronous versus asynchronous modeling of gene regulatory networks.
Bioinformatics, 2008

Stochastic modeling and analysis for environmentally powered wireless sensor nodes.
Proceedings of the 6th International Symposium on Modeling and Optimization in Mobile, 2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.
Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

System-level design technologies for heterogeneous distributed systems.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks.
Proceedings of the Design, Automation and Test in Europe, 2008

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.
Proceedings of the Design, Automation and Test in Europe, 2008

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008

Designing Micro/Nano Systems for a Safer and Healthier Tomorrow.
Proceedings of the Design, Automation and Test in Europe, 2008

Programmable logic circuits based on ambipolar CNFET.
Proceedings of the 45th Design Automation Conference, 2008

Reliability-aware design for nanometer-scale devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.
VLSI Design, 2007

Power and Reliability Management of SoCs.
IEEE Trans. VLSI Syst., 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.
IEEE Trans. VLSI Syst., 2007

HW-SW emulation framework for temperature-aware design in MPSoCs.
ACM Trans. Design Autom. Electr. Syst., 2007

Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics.
IEEE Trans. Information Technology in Biomedicine, 2007

Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.
Trans. HiPEAC, 2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

An Application-Specific Design Methodology for On-Chip Crossbar Generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Bringing NoCs to 65 nm.
IEEE Micro, 2007

An Application-Specific Design Methodology for STbus Crossbar Generation
CoRR, 2007

Clustering protein environments for function prediction: finding PROSITE motifs in 3D.
BMC Bioinformatics, 2007

Dynamic simulation of regulatory networks using SQUAD.
BMC Bioinformatics, 2007

Early wire characterization for predictable network-on-chip global interconnects.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments.
Proceedings of the Research in Computational Molecular Biology, 2007

NoC Design and Implementation in 65nm Technology.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Design Technologies for Networks on Chips.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

New Design Paradigms: New Architectures for New technologies.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

System-Level Design for Nano-Electronics.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Temperature-aware processor frequency assignment for MPSoCs using convex optimization.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Analysis and Optimization of MPSoC Reliability.
J. Low Power Electronics, 2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Routing and Message-Dependent Deadlock Free Networks on Chips.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Nanoelectronics: Challenges and Opportunities.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Routing Aware Switch Hardware Customization for Networks on Chips.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Mining Gene Sets for Measuring Similarities.
Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Reliability Support for On-Chip Memories Using Networks-on-Chip.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Designing application-specific networks on chips with floorplan information.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A simulation methodology for reliability analysis in multi-core SoCs.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A methodology for mapping multiple use-cases onto networks on chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.
Proceedings of the 43rd Design Automation Conference, 2006

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.
Proceedings of the 43rd Design Automation Conference, 2006

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

An opportunistic reconfiguration strategy for environmentally powered devices.
Proceedings of the Third Conference on Computing Frontiers, 2006

Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.
Proceedings of the 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS 2006), 2006

Mapping and configuration methods for multi-use-case networks on chips.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Network-on-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Embedded Systems Handbook., 2005

A robust self-calibrating transmission scheme for on-chip networks.
IEEE Trans. VLSI Syst., 2005

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
IEEE Trans. Parallel Distrib. Syst., 2005

Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams.
IEEE/ACM Trans. Comput. Biology Bioinform., 2005

Error control schemes for on-chip communication links: the energy-reliability tradeoff.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Design, Synthesis, and Test of Networks on Chips.
IEEE Design & Test of Computers, 2005

Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers, 2005

IEEE Council for Electronic Design Automation: A new beginning.
IEEE Design & Test of Computers, 2005

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.
IEEE Design & Test of Computers, 2005

Optimization of Reliability and Power Consumption in Systems on a Chip.
Proceedings of the Integrated Circuit and System Design, 2005

Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

Self-calibrating networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel approach for network on chip emulation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Prediction of regulatory modules comprising microRNAs and target genes.
Proceedings of the ECCB/JBI'05 Proceedings, Fourth European Conference on Computational Biology/Sixth Meeting of the Spanish Bioinformatics Network (Jornadas de BioInformática), Palacio de Congresos, Madrid, Spain, September 28, 2005

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
Proceedings of the 2005 Design, 2005

An Application-Specific Design Methodology for STbus Crossbar Generation.
Proceedings of the 2005 Design, 2005

A Complete Network-On-Chip Emulation Framework.
Proceedings of the 2005 Design, 2005

Performance driven reliable link design for networks on chips.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Network On-Chip Design for Gigascale Systems-on-Chip.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
Specification and analysis of power-managed systems.
Proceedings of the IEEE, 2004

Packetization and routing analysis of on-chip multiprocessor networks.
Journal of Systems Architecture, 2004

On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations.
IEEE Design & Test of Computers, 2004

Reliability and Power Management of Integrated Systems.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Bandwidth-Constrained Mapping of Cores onto NoC Architectures.
Proceedings of the 2004 Design, 2004

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.
Proceedings of the 2004 Design, 2004

SUNMAP: a tool for automatic topology selection and generation for NoCs.
Proceedings of the 41th Design Automation Conference, 2004

Reliable communication in systems on chips.
Proceedings of the 41th Design Automation Conference, 2004

Enhanced pClustering and Its Applications to Gene Expression Data.
Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

2003
Complex instruction and software library mapping for embedded software using symbolic algebra.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Application of symbolic computer algebra in high-level data-flow synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

CASS Brings Publishing to Its DAC Partnership.
IEEE Design & Test of Computers, 2003

Heterogeneous Wireless Network Management.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Robust System Design with Uncertain Information.
Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Packetized On-Chip Interconnect Communication Analysis for MPSoC.
Proceedings of the 2003 Design, 2003

Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Automatic Instruction Set Extension and Utilization for Embedded Processors.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

2002
Power-aware operating systems for interactive systems.
IEEE Trans. VLSI Syst., 2002

Dynamic frequency scaling with buffer insertion for mixed workloads.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Value-sensitive automatic code specialization for embedded software.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Dynamic Power Management for Nonstationary Service Requests.
IEEE Trans. Computers, 2002

Networks on Chips: A New SoC Paradigm.
IEEE Computer, 2002

An Adaptive Low-Power Transmission Scheme for On-Chip Networks.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Physical synthesis for ASIC datapath circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low Power Embedded Software Optimization Using Symbolic Algebra.
Proceedings of the 2002 Design, 2002

Networks on Chip: A New Paradigm for Systems on Chip Design.
Proceedings of the 2002 Design, 2002

Low Power Error Resilient Encoding for On-Chip Data Buses.
Proceedings of the 2002 Design, 2002

Analysis of power consumption on switch fabrics in network routers.
Proceedings of the 39th Design Automation Conference, 2002

Complex library mapping for embedded software using symbolic algebra.
Proceedings of the 39th Design Automation Conference, 2002

Readings in hardware / software co-design.
Morgan Kaufmann, ISBN: 978-1-55860-702-6, 2002

2001
Polynomial circuit models for component matching in high-level synthesis.
IEEE Trans. VLSI Syst., 2001

Energy-efficient design of battery-powered embedded systems.
IEEE Trans. VLSI Syst., 2001

Synthesis of hardware models in C with pointers and complex data structures.
IEEE Trans. VLSI Syst., 2001

Event-driven power management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001

Comparing System-Level Power Management Policies.
IEEE Design & Test of Computers, 2001

Cache-efficient memory layout of aggregate data structures.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Source code transformation based on software cost analysis.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic source code specialization for energy reduction.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Symbolic Algebra and Timing Driven Data-flow Synthesis.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Component selection and matching for IP-based design.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Voltage Scaling and Power Management for Portable Systems.
Proceedings of the 38th Design Automation Conference, 2001

Using Symbolic Algebra in Algorithmic Level DSP Synthesis.
Proceedings of the 38th Design Automation Conference, 2001

2000
Glitch power minimization by selective gate freezing.
IEEE Trans. VLSI Syst., 2000

A survey of design techniques for system-level dynamic power management.
IEEE Trans. VLSI Syst., 2000

Regression-based RTL power modeling.
ACM Trans. Design Autom. Electr. Syst., 2000

Synthesis of low-power selectively-clocked systems from high-level specification.
ACM Trans. Design Autom. Electr. Syst., 2000

System-level power optimization: techniques and tools.
ACM Trans. Design Autom. Electr. Syst., 2000

A multilevel engine for fast power simulation of realistic inputstreams.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems.
Design Autom. for Emb. Sys., 2000

Dynamic power management for portable systems.
Proceedings of the MOBICOM 2000, 2000

Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Requester-Aware Power Reduction.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Energy efficient design of portable wireless systems.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Do our low-power tools have enough horse power? (panel session) (title only).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Operating-system directed power reduction.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Data Path Placement with Regularity.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Dynamic Power Management of Laptop Hard Disk.
Proceedings of the 2000 Design, 2000

Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C.
Proceedings of the 2000 Design, 2000

Quantitative Comparison of Power Management Algorithms.
Proceedings of the 2000 Design, 2000

Low-power task scheduling for multiple devices.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.
ACM Trans. Design Autom. Electr. Syst., 1999

Policy optimization for dynamic power management.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.
IEEE Trans. Computers, 1999

Event-Driven Power Management of Portable Systems.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Energy-efficient design of battery-powered embedded systems.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Efficient switching activity computation during high-level synthesis of control-dominated designs.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

System-level power optimization: techniques and tools.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Dynamic power management using adaptive learning tree.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Adaptive Hard Disk Power Management on Personal Computers.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Polynomial Methods for Allocating Complex Components.
Proceedings of the 1999 Design, 1999

Hardware Synthesis from C/C++ Models.
Proceedings of the 1999 Design, 1999

Dynamic Power Management for non-stationary service requests.
Proceedings of the 1999 Design, 1999

Glitch Power Minimization by Gate Freezing.
Proceedings of the 1999 Design, 1999

Cycle-Accurate Simulation of Energy Consumption in Embedded Systems.
Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.
Proceedings of the 36th Conference on Design Automation, 1999

Software controlled power management.
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998
Power optimization of core-based systems by address bus encoding.
IEEE Trans. VLSI Syst., 1998

Iterative remapping for logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1998

Regression Models for Behavioral Power Estimation.
Integrated Computer-Aided Engineering, 1998

Polynomial methods for component matching and verification.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Finding all simple disjunctive decompositions using irredundant sum-of-products forms.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Dynamic power management of electronic systems.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.
Proceedings of the Field-Programmable Logic and Applications, 1998

Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III.
Proceedings of the 24th EUROMICRO '98 Conference, 1998

Characterization-Free Behavioral Power Modeling.
Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.
Proceedings of the 1998 Design, 1998

Automated Composition of Hardware Components.
Proceedings of the 35th Conference on Design Automation, 1998

Policy Optimization for Dynamic Power Management.
Proceedings of the 35th Conference on Design Automation, 1998

Computational Kernels and their Application to Sequential Power Optimization.
Proceedings of the 35th Conference on Design Automation, 1998

Dynamic power management - design techniques and CAD tools.
Kluwer, ISBN: 978-0-7923-8086-3, 1998

1997
Clock Skew Optimization for Peak Current Reduction.
VLSI Signal Processing, 1997

Gate-level power and current simulation of CMOS integrated circuits.
IEEE Trans. VLSI Syst., 1997

A survey of Boolean matching techniques for library binding.
ACM Trans. Design Autom. Electr. Syst., 1997

Specification and analysis of timing constraints for embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1997

Constrained software synthesis for embedded applications.
Journal of Systems Architecture, 1997

Re-mapping for low power under tight timing constraints.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

System-level power optimization of special purpose applications: the beach solution.
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Generalized matching from theory to application.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast power estimation for deterministic input streams.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Adaptive least mean square behavioral power modeling.
Proceedings of the European Design and Test Conference, 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.
Proceedings of the European Design and Test Conference, 1997

1996
Scheduling and control generation with environmental constraints based on automata representations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Analysis and synthesis of concurrent digital circuits using control-flow expressions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

Automatic synthesis of low-power gated-clock finite-state machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996

A co-synthesis approach to embedded system design automation.
Design Autom. for Emb. Sys., 1996

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.
Proceedings of the 9th International Symposium on System Synthesis, 1996

Clock skew optimization for peak current reduction.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Gate-level current waveform simulation of CMOS integrated circuits.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Distributed EDA Tool Integration: The PPP Paradigm.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Synthesis from mixed specifications.
Proceedings of the conference on European design automation, 1996

Design for Testability of Gated-Clock FSMs.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Optimization of combinational logic circuits based on compatible gates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995

Transformation and synthesis of FSMs for low-power gated-clock implementation.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994
Computer-aided hardware-software codesign.
IEEE Micro, 1994

Saving Power by Synthesizing Gated Clocks for Sequential Circuits.
IEEE Design & Test of Computers, 1994

Program Implementation Schemes for Hardware-Software Systems.
IEEE Computer, 1994

A Synthesis Framework Based on Trace and Automata Theory.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Decomposition methods for library binding of speed-independent asynchronous designs.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Scheduling with Environmental Constraints based on Automata Representations.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Constrained software generation for hardware-software systems.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Redesigning hardware-software systems.
Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993
Interface optimization for concurrent systems under timing constraints.
IEEE Trans. VLSI Syst., 1993

Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Algorithms for technology mapping based on binary decision diagrams and on Boolean operations.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Don't care set specifications in combinational and synchronous logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993

Hardware-Software Cosynthesis for Digital Systems.
IEEE Design & Test of Computers, 1993

High-Level Synthesis of Digital Circuits.
Advances in Computers, 1993

Modeling hierarchical combinational circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

Optimization of Combinational Logic Circuits Based on Compatible Gates.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

Optimizing the control-unit through the resynchronization of operations.
Integration, 1992

Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components.
Proceedings of the 29th Design Automation Conference, 1992

Recurrence Equations and the Optimization of Synchronous Logic Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
Synchronous logic synthesis: algorithms for cycle-time minimization.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1991

Optimal synthesis of control logic from behavioral specifications.
Integration, 1991

Constrained resource sharing and conflict resolution in Hebe.
Integration, 1991

Technology mapping for a two-output RAM-based field programmable gate array.
Proceedings of the conference on European design automation, 1991

Control Optimization Based on Resynchronization of Operations.
Proceedings of the 28th Design Automation Conference, 1991

Technology Mapping for Electrically Programmable Gate Arrays.
Proceedings of the 28th Design Automation Conference, 1991

1990
The Olympus Synthesis System.
IEEE Design & Test of Computers, 1990

Guest Editorial: High-Level Synthesis of Digital Circuits.
IEEE Design & Test of Computers, 1990

Partitioning of Functional Models of Synchronous Digital Systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Observability Don't Care Sets and Boolean Relations.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Technology mapping using boolean matching and don't care sets.
Proceedings of the European Design Automation Conference, 1990

Relative Scheduling Under Timing Constraints.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Inserting active delay elements to achieve wave pipelining.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
HERCULES - a System for High-Level Synthesis.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987
Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1987

1986
Correction to "Optimal State Assignment for Finite State Machines".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1986

1985
Optimal State Assignment for Finite State Machines.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1985

1984
Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications".
IEEE Trans. on CAD of Integrated Circuits and Systems, 1984

1983
Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1983

Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1983

PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays.
Proceedings of the 20th Design Automation Conference, 1983


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