Yusuf Leblebici
According to our database1,
Yusuf Leblebici
authored at least 294 papers
between 1988 and 2022.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2010, "For contributions to reliability and design techniques for integrated circuits and systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on ece.wpi.edu
On csauthors.net:
Bibliography
2022
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI.
IEEE Trans. Very Large Scale Integr. Syst., 2021
An 8-Bit 800 MS/s Loop-Unrolled SAR ADC With Common-Mode Adaptive Background Offset Calibration in 28 nm FDSOI.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI.
Microelectron. J., 2021
A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
Real-time high-resolution omnidirectional imaging platform for drone detection and tracking.
J. Real Time Image Process., 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Discrete Time Analysis of Phase Detector Timing Nonidealities in Type-I Sub-Sampling PLL.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
Proceedings of the Handbook of Memristor Networks., 2019
2018
IEEE Trans. Circuits Syst. Video Technol., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.
IEEE J. Solid State Circuits, 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels.
IEEE J. Solid State Circuits, 2018
Generalization of Referenceless Timing Mismatch Calibration Methods for Time-Interleaved ADCs.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
The key impact of incorporated Al2O3 barrier layer on W-based ReRAM switching performance.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
System Level simulation framework for the ASICs development of a novel particle physics detector.
Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018
Proceedings of the Non-Volatile Memory Technology Symposium, 2018
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
A 56Gb/s burst-mode NRZ optical receiver with 6.8ns power-on and CDR-Lock time for adaptive optical links in 14nm FinFET CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Online Feature Learning from a non-i.i.d. Stream in a Neuromorphic System with Synaptic Competition.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018
An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Neuromorphic Architecture With 1M Memristive Synapses for Detection of Weakly Correlated Inputs.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
A Time-Division Multiplexing Signaling Scheme for Inter-Symbol/Channel Interference Reduction in Low-Power Multi-Drop Memory Links.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
Design and Modeling of Serial Data Transceiver Architecture by Employing Multi-Tone Single-Sideband Signaling Scheme.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
IEEE Trans. Biomed. Circuits Syst., 2017
IEEE J. Solid State Circuits, 2017
Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies.
Integr., 2017
Proceedings of the 17th Non-Volatile Memory Technology Symposium, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 12th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Neuromorphic system with phase-change synapses for pattern learning and feature extraction.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Feature Learning Using Synaptic Competition in a Dynamically-Sized Neuromorphic Architecture.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2017, 2017
Evolution of oxygen vacancies under electrical characterization for HfOx-based ReRAMs.
Proceedings of the 47th European Solid-State Device Research Conference, 2017
Proceedings of the Computing Frontiers Conference, 2017
2016
A Digital Spectrum Shaping Signaling Serial-Data Transceiver With Crosstalk and ISI Reduction Property in Multidrop Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2016
Microelectron. J., 2016
Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.
Microelectron. J., 2016
Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS.
IEEE J. Solid State Circuits, 2016
A 4×9 Gb/s 1pJ/b Hybrid NRZ/Multi-Tone I/O With Crosstalk and ISI Reduction for Dense Interconnects.
IEEE J. Solid State Circuits, 2016
J. Real Time Image Process., 2016
Neurocomputing, 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
A 16-channel 1.1mm<sup>2</sup> implantable seizure control SoC with sub-μW/channel consumption and closed-loop stimulation in 0.18µm CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A wideband MDLL with jitter reduction scheme for forwarded clock serial links in 40 nm CMOS.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
A fully-digital spectrum shaping signaling for serial-data transceiver with crosstalk and ISI reduction property in multi-drop memory interfaces.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
Architectural modeling of a multi-tone/single-sideband serial link transceiver for lossy wireline data links.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
Copper TSV-based die-level via-last 3D integration process with parylene-C adhesive bonding technique.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
A Real-Time Multiaperture Omnidirectional Visual Sensor Based on an Interconnected Network of Smart Cameras.
IEEE Trans. Circuits Syst. Video Technol., 2015
Analysis and Characterization of Variability in Subthreshold Source-Coupled Logic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
A comparative experimental investigation on responsivity and response speed of photo-diode and photo-BJT structures integrated in a low-cost standard CMOS process.
Microelectron. J., 2015
A sub-mW pulse-based 5-bit flash ADC with a time-domain fully-digital reference ladder.
Microelectron. J., 2015
IEEE J. Solid State Circuits, 2015
A subthreshold current-sensing ΣΔ modulator for low-voltage and low-power sensor interfaces.
Int. J. Circuit Theory Appl., 2015
Int. J. Circuit Theory Appl., 2015
A 4×9 Gb/s 1 pJ/b NRZ/multi-tone serial-data transceiver with crosstalk reduction architecture for multi-drop memory interfaces in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Design optimization of polyphase digital down converters for extremely high frequency wireless communications.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Trinocular adaptive window size disparity estimation algorithm and its real-time hardware.
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the Real-Time Image and Video Processing 2015, 2015
Full swing 20 GHz frequency divider with 1 V supply voltage in FD-SOI 28 nm technology.
Proceedings of the Nordic Circuits and Systems Conference, 2015
3.6 GHz CMOS ring oscillator with low tune voltage sensitivity and temperature compensation.
Proceedings of the Nordic Circuits and Systems Conference, 2015
10.3 A 7.5mW 7.5Gb/s mixed NRZ/multi-tone serial-data transceiver for multi-drop memory interfaces in 40nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Jitter analysis and measurement in subthreshold source-coupled differential ring oscillators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Low-voltage read/write circuit design for transistorless ReRAM crossbar arrays in 180nm CMOS technology.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Live demonstration: Real-time free viewpoint synthesis using three-camera disparity estimation hardware.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A low-power 490 mpixels/s hardware accelerator for pyramidal decomposition of images.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015
Proceedings of the 9th International Conference on Distributed Smart Camera, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 6th IEEE International Workshop on Computational Advances in Multi-Sensor Adaptive Processing, 2015
2014
J. Signal Process. Syst., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Dynamically adaptive real-time disparity estimation hardware using iterative refinement.
Integr., 2014
Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
A 5.43-μW 0.8-V subthreshold current-sensing ΣΔ modulator for low-noise sensor interfaces.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
A retina-inspired robust on-focal-plane multi-band edge-detection scheme for CMOS image sensors.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An Immersive Telepresence System Using a Real-Time Omnidirectional Camera and a Virtual Reality Head-Mounted Display.
Proceedings of the 2014 IEEE International Symposium on Multimedia, 2014
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014
A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm<sup>2</sup> in 32 nm SOI CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
J. Signal Process. Syst., 2013
A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS.
IEEE J. Solid State Circuits, 2013
A Scalable and Adaptive Technique for Compensating Process Variations and Controlling Leakage and Delay in the FPGA.
J. Low Power Electron., 2013
Hemispherical Multiple Camera System for High Resolution Omni-Directional Light Field Imaging.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Spherical Panorama Construction Using Multi Sensor Registration Priors and Its Real-Time Hardware.
Proceedings of the 2013 IEEE International Symposium on Multimedia, 2013
A low-power area-efficient compressive sensing approach for multi-channel neural recording.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
High frame-rate low-power compressive sampling CMOS image sensor architecture: [extended abstract].
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
A hardware-oriented dynamically adaptive disparity estimation algorithm and its real-time hardware.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.
Proceedings of the Design, Automation and Test in Europe, 2013
Fast and accurate BER estimation methodology for I/O links based on extreme value theory.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
A spherical multi-camera system with real-time omnidirectional video acquisition capability.
IEEE Trans. Consumer Electron., 2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
High-Level Energy Estimation in the Sub-V$_{{\rm T}}$ Domain: Simulation and Measurement of a Cardiac Event Detector.
IEEE Trans. Biomed. Circuits Syst., 2012
Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.
Proc. IEEE, 2012
Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Real-Time FPGA Implementation of Linear Blending Vision Reconstruction Algorithm Using a Spherical Light Field Camera.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Design techniques and analysis of high-resolution neural recording systems targeting epilepsy focus localization.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Design and Implementation of Multi-camera Systems Distributed over a Spherical Geometry.
Proceedings of the Diagrammatic Representation and Inference, 2012
Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2011
Low-Power and Widely Tunable Linearized Biquadratic Low-Pass Transconductor-C Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor.
IEEE Trans. Biomed. Circuits Syst., 2011
Optimal Logic Architecture and Supply Voltage Selection Method to Reduce the Impact of the Threshold Voltage Variation on the Timing.
J. Low Power Electron., 2011
IEICE Electron. Express, 2011
Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library.
Proceedings of the 48th Design Automation Conference, 2011
2010
Microelectron. J., 2010
Optimization of the wire grid size for differential routing: Analysis and impact on the power-delay-area tradeoff.
Microelectron. J., 2010
Nanowatt Range Folding-Interpolating Analog-to-Digital Converter Using Subthreshold Source-Coupled Circuits.
J. Low Power Electron., 2010
Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields.
IET Inf. Secur., 2010
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Output probability density functions of logic circuits: Modeling and fault-tolerance evaluation.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random V<sub>T</sub> Variations on Timing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Selective redundancy-based design techniques for the minimization of local delay variations.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A (256×256) pixel 76.7mW CMOS imager/ compressor based on real-time In-pixel compressive sensing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
A 9 pW/Hz adjustable clock generator with 3-decade tuning range for dynamic power management in subthreshold SCL systems.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Subthreshold current-mode oscillator-based quantizer with 3-decade scalable sampling rate and pico-Ampere range resolution.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Ultra-low power mixed-signal design platform using subthreshold source-coupled circuits.
Proceedings of the Design, Automation and Test in Europe, 2010
AVGS-Mux style: A novel technology and device independent technique for reducing power and compensating process variations in FPGA fabrics.
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
ACM Trans. Reconfigurable Technol. Syst., 2009
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology.
Trans. Comput. Sci., 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP.
Microelectron. J., 2009
IEEE J. Solid State Circuits, 2009
Electrical modeling of the cell-electrode interface for recording neural activity from high-density microelectrode arrays.
Neurocomputing, 2009
Int. J. Nanotechnol. Mol. Comput., 2009
Int. J. Nanotechnol. Mol. Comput., 2009
A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime.
Int. J. Circuit Theory Appl., 2009
Energy Dissipation Reduction of a Cardiac Event Detector in the Sub-V<sub><i>t</i></sub> Domain By Architectural Folding.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Proceedings of the Nano-Net - 4th International ICST Conference, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Optimization of Wire Grid Size for Differential Routing and Impact on the Power-delay-area Tradeoff.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons.
Proceedings of the International Joint Conference on Neural Networks, 2009
Memory organization and data layout for instruction set extensions with architecturally visible storage.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 35th European Solid-State Circuits Conference, 2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR).
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
Proceedings of the Cryptographic Hardware and Embedded Systems, 2009
Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.
Proceedings of the 2009 International Conference on Compilers, 2009
A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
CMOS realization of two-dimensional mixed analog-digital Hamming distance discriminator circuits for real-time imaging applications.
Microelectron. J., 2008
IEEE J. Solid State Circuits, 2008
Energy Efficiency Comparison of Asynchronous and Synchronous Circuits Operating in the Sub-Threshold Regime.
J. Low Power Electron., 2008
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Reverse Vgs Static CMOS (RVGS-SCMOS); A New Technique for Dynamically Compensating the Process Variations in Sub-threshold Designs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008
Improving the power-delay product in SCL circuits using source follower output stage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
Proceedings of the 2008 International Conference on Compilers, 2008
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008
2007
A Power-Efficient Clock and Data Recovery Circuit in 0.18 µm CMOS Technology for Multi-Channel Short-Haul Optical Data Communication.
IEEE J. Solid State Circuits, 2007
On-Line Global Energy Optimization in Multi-Core Systems Using Principles of Analog Computation.
IEEE J. Solid State Circuits, 2007
J. Low Power Electron., 2007
Proceedings of the 2007 IEEE International SOC Conference, 2007
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007
A Simulation-Based Methodology for Evaluating the DPA-Resistance of Cryptographic Functional Units with Application to CMOS and MCML Technologies.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply Voltage.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the 18th European Conference on Circuit Theory and Design, 2007
2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Analysis and modeling of jitter and frequency tolerance in gated oscillator based CDRs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density.
Proceedings of the International Joint Conference on Neural Networks, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
2005
On the fault tolerance of a clustered single-electron neural network for differential enhancement.
IEICE Electron. Express, 2005
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Limiting amplifiers for next-generation multi-channel optical I/0 interfaces in SoCs.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Quantitative modelling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the Forum on specification and Design Languages, 2005
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
A multichannel 3.5mW/Gbps/channel gated oscillator based CDR in a 0.18μm digital CMOS technology.
Proceedings of the 31st European Solid-State Circuits Conference, 2005
Top-Down Design of a Low-Power Multi-Channel 2.5-Gbit/s/Channel Gated Oscillator Clock-Recovery Circuit.
Proceedings of the 2005 Design, 2005
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
2004
Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Providing QoS to connection-less packet-switched NoC by implementing DiffServ functionalities.
Proceedings of the 2004 International Symposium on System-on-Chip, 2004
Robust and fault-tolerant circuit design for nanometer-scale devices and single-electron transistors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Modelling and implementation of twisted differential on-chip interconnects for crosstalk noise reduction.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Mixed analog-digital image processing circuit based on Hamming artificial neural network architecture.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic.
Proceedings of the Second IASTED International Conference on Circuits, 2004
Low noise MCML prefix adders using 0.18 µm CMOS technology.
Proceedings of the Second IASTED International Conference on Circuits, 2004
A 4-channel 2.5Gb/s/channel 66dBΩ inductorless transimpedance amplifier [optical receiver applications].
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
A Highly Fault Tolerant PLA Architecture for Failure-Prone Nanometer CMOS and Novel Quantum Device Technologies.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
Twisted differential on-chip interconnect architecture for inductive/capacitive crosstalk noise cancellation.
Proceedings of the 2003 International Symposium on System-on-Chip, 2003
Design and realization of a modular 200 MSample/s 12-bit pipelined A/D converter block using deep-submicron digital CMOS technology.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Full-custom CMOS realization of a high-performance binary sorting engine with linear area-time complexity.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
VLSI Realization of a Two-Dimensional Hamming Distance Comparator ANN for Image Processing Applications.
Proceedings of the 11th European Symposium on Artificial Neural Networks, 2003
2000
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic.
VLSI Design, 2000
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
1999
A novel analog-digital flash converter architecture based on capacitive threshold gates.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the International Joint Conference Neural Networks, 1999
1996
A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates.
IEEE J. Solid State Circuits, 1996
Design considerations for CMOS digital circuits with improved hot-carrier reliability.
IEEE J. Solid State Circuits, 1996
1993
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
1992
Modeling of nMOS transistors for simulation of hot-carrier-induced device and circuit degradation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
1991
Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability
PhD thesis, 1991
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991
1990
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990
1989
Simulation of MOS circuit performance degradation with emphasis on VLSI design-for-reliability.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989
1988
An efficient method for circuit sensitivity calculation using piecewise linear waveform models.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988