M. Haykel Ben Jamaa

According to our database1, M. Haykel Ben Jamaa authored at least 26 papers between 2007 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits.
IEEE Des. Test, 2016

2014
Using TSVs for thermal mitigation in 3D circuits: Wish and truth.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Thermal correlation between measurements and FEM simulations in 3D ICs.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2011
Regular Nanofabrics in Emerging Technologies - Design and Fabrication Methods for Nanoscale Digital Circuits
Lecture Notes in Electrical Engineering 82, Springer, ISBN: 978-94-007-0649-1, 2011

An Efficient Gate Library for Ambipolar CNTFET Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Ultra-fine grain FPGAs: A granularity study.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Evaluation of a crossbar multiplexer in a lithography-based nanowire technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Can we go towards true 3-D architectures?
Proceedings of the 48th Design Automation Conference, 2011

2010
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Reducing transistor count in clocked standard cells with ambipolar double-gate FETs.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Memristive devices fabricated with silicon nanowire schottky barrier transistors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Characterization of memristive Poly-Si Nanowires via empirical physical modelling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Synthesis of regular computational fabrics with ambipolar CNTFET technology.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Emerging memory technologies for reconfigurable routing in FPGA architecture.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Phase-change-memory-based storage elements for configurable logic.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Power consumption of logic circuits in ambipolar carbon nanotube technology.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.
Proceedings of the Design, Automation and Test in Europe, 2009

Decoding nanowire arrays fabricated with the multi-spacer patterning technique.
Proceedings of the 46th Design Automation Conference, 2009

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.
Proceedings of the 2009 International Conference on Compilers, 2009

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Programmable logic circuits based on ambipolar CNFET.
Proceedings of the 45th Design Automation Conference, 2008

2007
Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Interactive presentation: Improving the fault tolerance of nanometric PLA designs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007


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