Konrad Möller

Orcid: 0000-0001-5709-603X

Affiliations:
  • University of Kassel, Germany


According to our database1, Konrad Möller authored at least 15 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018
Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ILP-Based Modulo Scheduling and Binding for Register Minimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Run-time Reconfigurable Constant Multiplication on Field Programmable Gate Arrays.
PhD thesis, 2017

Reconfigurable Constant Multiplication for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2017

Model-based hardware design based on compatible sets of isomorphic subgraphs.
Proceedings of the International Conference on Field Programmable Technology, 2017

2015
Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits.
CoRR, 2015

2014
Dynamically Reconfigurable Constant Multiplication on FPGAs.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, 2014

Pipelined reconfigurable multiplication with constants on FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

2013
FIR filter optimization for video processing on FPGAs.
EURASIP J. Adv. Signal Process., 2013

Dynamically reconfigurable FIR filter architectures with fast reconfiguration.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013

Reconfigurable FIR filter using distributed arithmetic on FPGAs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


  Loading...