Kulbhushan Sharma
Orcid: 0000-0001-9948-6781
According to our database1,
Kulbhushan Sharma authored at least 10 papers
between 2021 and 2026.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2026
Highly robust power efficient Full Adder and Full Subtractor CiM architecture using 10T SRAM cell.
Integr., 2026
Design of a low-power bulk-driven double differential pair OTA with enhanced transconductance and CMRR.
Integr., 2026
Design of a soft error resilient 13T SRAM architecture for radiation-prone environments in FinFET 18 nm technology.
Integr., 2026
2025
One-Sided Schmitt-Trigger-Based Low Power Read Decoupled 11T CNTFET SRAM with Improved Stability.
Circuits Syst. Signal Process., February, 2025
Design of a SRAM memory cell with enhanced stability and variability for embedded biomedical applications.
Integr., 2025
Ultra-low power linearized FVF based BD double diffusor double differential pair transconductor.
Integr., 2025
2024
Read Improved and Low Leakage Power CNTFET Based Hybrid 10t SRAM Cell for Low Power Applications.
Circuits Syst. Signal Process., March, 2024
2023
J. Circuits Syst. Comput., November, 2023
2022
A Low-Noise High-Gain Recycling Folded Cascode Operational Transconductance Amplifier Based on Gate Driven and Quasi-Floating Bulk Technique.
J. Circuits Syst. Comput., 2022
2021
MOS based pseudo-resistors exhibiting Tera Ohms of Incremental Resistance for biomedical applications: Analysis and proof of concept.
Integr., 2021