Kun Yuan

Affiliations:

Facebook Inc., San Jose, CA, USA
University of Texas at Austin, Electrical and Computer Engineering Department, Austin, TX, USA (PhD 2010)

According to our database¹, Kun Yuan authored at least 17 papers between 2007 and 2016.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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PhD thesis

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Bibliography

2016

EBL Overlapping Aware Stencil Planning for MCC System.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

2015

Layout Decomposition for Triple Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2013

E-BLOW: e-beam lithography overlapping aware stencil planning for MCC system.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters.

[BibT_eX]

[DOI]

Kun Yuan

Bei Yu

David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper).

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

2011

E-beam lithography stencil planning and optimization with overlapped characters.

[BibT_eX]

[DOI]

Kun Yuan

David Z. Pan

Proceedings of the 2011 International Symposium on Physical Design, 2011

Layout decomposition for triple patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization.

[BibT_eX]

[DOI]

Kun Yuan

Jae-Seok Yang

David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Manufacturability Aware Routing in Nanometer VLSI.

[BibT_eX]

[DOI]

David Z. Pan

Minsik Cho

Kun Yuan

Found. Trends Electron. Des. Autom., 2010

WISDOM: Wire spreading enhanced decomposition of masks in Double Patterning Lithography.

[BibT_eX]

[DOI]

Kun Yuan

David Z. Pan

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Double patterning lithography friendly detailed routing with redundant via consideration.

[BibT_eX]

[DOI]

Kun Yuan

Katrina Lu

David Z. Pan

Proceedings of the 46th Design Automation Conference, 2009

2008

ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

BoxRouter 2.0: architecture and implementation of a hybrid and robust global router.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Kun Yuan

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