Kyuchull Kim

According to our database, Kyuchull Kim authored at least 6 papers between 1990 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Low-Area Wrapper Cell Design for Hierarchical SoC Testing.

Kyuchull Kim, Kewal K. Saluja

J. Electron. Test., 2009

1996

HYSIM: Hybrid Fault Simulation for Synchronous Sequential Circuits.

Kyuchull Kim, Kewal K. Saluja

VLSI Design, 1996

1995

Fast computation of MISR signatures.

Manoj Franklin, Kewal K. Saluja, Kyuchull Kim

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

1993

CCSTG: an efficient test pattern generator for sequential circuits.

Kyuchull Kim, Kewal K. Saluja

Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992

On fault deletion problem in concurrent fault simulation for synchronous sequential circuits.

Kyuchull Kim, Kewal K. Saluja

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1990

Improved Test Generation for High-Activity Circuits.

Kewal K. Saluja, Kyuchull Kim

IEEE Des. Test Comput., 1990