Manoj Franklin

Affiliations:
  • University of Maryland, College Park, USA


According to our database1, Manoj Franklin authored at least 69 papers between 1989 and 2020.

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Bibliography

2020
Indoor Route and Location Inference using Smartphone IMU Sensors.
Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020

2011
Teaching computer architecture with a graphical PC simulator.
Proceedings of the 16th Annual SIGCSE Conference on Innovation and Technology in Computer Science Education, 2011

2010
Speculative-aware execution: a simple and efficient technique for utilizing multi-cores to improve single-thread performance.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2008
Hierarchical Verification for Increasing Performance in Reliable Processors.
J. Electron. Test., 2008

HMMer-Cell: High Performance Protein Profile Searching on the Cell/B.E. Processor.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2008

2007
Non-Inclusion Property in Multi-Level Caches Revisited.
Int. J. Comput. Their Appl., 2007

Prioritizing verification via value-based correctness criticality.
Proceedings of the 25th International Conference on Computer Design, 2007

2006
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

The Filter Checker: An Active Verification Management Approach.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

RHT: A Context-Based Return Address Predictor.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Scalability Aspects of Instruction Distribution Algorithms for Clustered Processors.
IEEE Trans. Parallel Distributed Syst., 2005

Instruction Replication for Reducing Delays Due to Inter-PE Communication Latency.
IEEE Trans. Computers, 2005

BioBench: A Benchmark Suite of Bioinformatics Applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

SST: Symbolic Subordinate Threading.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Neural Confidence Estimation for More Accurate Value Prediction.
Proceedings of the High Performance Computing, 2005

2004
A General Compiler Framework for Speculative Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 2004

Defining Wakeup Width for Efficient Dynamic Scheduling.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

A fast approximate interprocedural analysis for speculative multithreading compilers.
Proceedings of the 17th Annual International Conference on Supercomputing, 2003

Dynamic Thread Resizing for Speculative Multithreaded Processors.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Energy Efficient Asymmetrically Ported Register Files.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
A general compiler framework for speculative multithreading.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002

A Feasibility Study of Hierarchical Multithreading.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Hierarchical Interconnects for On-Chip Clustering.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Return-Address Prediction in Speculative Multithreaded Environments.
Proceedings of the High Performance Computing, 2002

Using Dataflow Based Contextfor Accurate Branch Prediction.
Proceedings of the High Performance Computing, 2002

Exploiting Data Value Prediction in Compiler Based Thread Formation.
Proceedings of the High Performance Computing, 2002

A Register File Architecture and Compilation Scheme for Clustered ILP Processors.
Proceedings of the Euro-Par 2002, 2002

2001
Balancing thoughput and fairness in SMT processors.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

An empirical study of the scalability aspects of instruction distribution algorithms for clustered processors.
Proceedings of the 2001 IEEE International Symposium on Performance Analysis of Systems and Software, 2001

Boosting SMT Performance by Speculation Control.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Putting Data Value Predictors to Work in Fine-Grain Parallel Processors.
Proceedings of the High Performance Computing - HiPC 2001, 8th International Conference, 2001

Using Dataflow Based Context for Accurate Value Prediction.
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 2001

2000
Branch Prediction in Multi-Threaded Processors.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors.
IEEE Trans. Parallel Distributed Syst., 1999

Performance Benefits of Exploiting Control Independence.
Proceedings of the High Performance Computing, 1999

Improving Data Value Prediction Accuracy Using Path Correlation.
Proceedings of the High Performance Computing, 1999

1998
Techniques for performing highly accurate data value prediction.
Microprocess. Microsystems, 1998

The PEWs microarchitecture: reducing complexity through data-dependence based decentralization.
Microprocess. Microsystems, 1998

Control flow prediction with unbalanced tree-like subgraphs.
Proceedings of the 5th International Conference On High Performance Computing, 1998

Available parallelism with data value prediction.
Proceedings of the 5th International Conference On High Performance Computing, 1998

An Empirical Study of Decentralized ILP Execution Models.
Proceedings of the ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, 1998

1997
Highly Accurate Data Value Prediction Using Hybrid Predictors.
Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, 1997

Multiscalar Execution along a Single Flow of Control.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Highly accurate data value prediction.
Proceedings of the Fourth International on High-Performance Computing, 1997

1996
Testing reconfigured RAM's and scrambled address RAM's for pattern sensitive faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

ARB: A Hardware Mechanism for Dynamic Reordering of Memory References.
IEEE Trans. Computers, 1996

PEWs: A Decentralized Dynamic Scheduler for ILP Processing.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

A study of dynamic scheduling techniques for multiscalar processors.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

Incorporating fault tolerance in superscalar processors.
Proceedings of the 3rd International Conference on High Performance Computing, 1996

1995
Fast computation of MISR signatures.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Improving CISC instruction decoding performance using a fill unit.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Control flow prediction with tree-like subgraphs for superscalar processors.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Incorporating Fault Tolerance in the Multiscalar Fine-Grain Parallel Processor.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

A study of time redundant fault tolerance techniques for superscalar processors.
Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

Fast computation of C-MISR signatures.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Hypergraph Coloring and Reconfigured RAM Testing.
IEEE Trans. Computers, 1994

An Algorithm to Test Reconfigured RAMs.
Proceedings of the Seventh International Conference on VLSI Design, 1994

A fill-unit approach to multiple instruction issue.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993
Control flow prediction for dynamic ILP processors.
Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors.
Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism.
Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, 1992

1991
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Pattern Sensitive Fault Testing of RAMs with Bullt-in ECC.
Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

High-Bandwidth Data Memory Systems for Superscalar Processors.
Proceedings of the ASPLOS-IV Proceedings, 1991

1990
Built-in Self-testing of Random-Access Memories.
Computer, 1990

1989
Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.
Proceedings of the Proceedings International Test Conference 1989, 1989

A study of time-redundant fault tolerance techniques for high-performance pipelined computers.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

Row/column pattern sensitive fault detection in RAMs via built-in self-test.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989


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