L. Hemanth Krishna

According to our database, L. Hemanth Krishna authored at least 12 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

Low Complexity Three's Complement Parallel Multiplier Using Special Operators of Ternary Logic.

L. Hemanth Krishna, B. Srinivasu, K. Sridharan

IEEE Trans. Circuits Syst. II Express Briefs, November, 2025

Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications.

L. Hemanth Krishna, Srinivasu Bodapati, Sreehari Veeramachaneni, Bhaskara Rao Jammu, Noor Mahammad Sk

CoRR, October, 2025

Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication.

Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu

CoRR, September, 2025

Low Power Approximate Multiplier Architecture for Deep Neural Networks.

Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu

CoRR, September, 2025

Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor.

L. Hemanth Krishna, Sreehari Veeramachaneni, Srinivasu Bodapati, Bhaskara Rao Jammu, Sk. Noor Mahammad

Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024

Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor.

L. Hemanth Krishna, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad

IEEE Embed. Syst. Lett., June, 2024

Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks.

L. Hemanth Krishna, B. Srinivasu

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers.

L. Hemanth Krishna, Nandit Kaushik, Srinivasu Bodapati

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

High-Speed Serial and Semi-Parallel IMPLY-based Approximate Adders through Memristors for In-Memory Computing.

Nandit Kaushik, L. Hemanth Krishna, Srinivasu Bodapati

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2021

Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication.

L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad

IET Comput. Digit. Tech., 2021

Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications.

L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications.

L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad

Proceedings of the 28th IEEE International Conference on Electronics, 2021