L. Hemanth Krishna

Orcid: 0000-0002-7737-6685

According to our database1, L. Hemanth Krishna authored at least 8 papers between 2021 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor.
Proceedings of the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems, 2025

2024
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor.
IEEE Embed. Syst. Lett., June, 2024

Approximate Ternary Matrix Multiplication for Image Processing and Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Energy Efficient Accurate and Approximate Modified Adders for Ternary Multipliers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

High-Speed Serial and Semi-Parallel IMPLY-based Approximate Adders through Memristors for In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2021
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication.
IET Comput. Digit. Tech., 2021

Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications.
Proceedings of the 28th IEEE International Conference on Electronics, 2021


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