Tsutomu Sasao
According to our database1,
Tsutomu Sasao
authored at least 242 papers
between 1975 and 2023.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1994, "For contributions to the design theory and techniques of combinational logic circuits.".
Timeline
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On csauthors.net:
Bibliography
2023
FLAP, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
2022
A Fast Method for Exactly Optimum Linear Decomposition of Index Generation Functions.
J. Multiple Valued Log. Soft Comput., 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
LUT Cascade Realization of Threshold Functions and Its Application to Implementation of Ternary Weight Neural Networks.
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
Proceedings of the 52nd IEEE International Symposium on Multiple-Valued Logic, 2022
2021
Realization of Multi-Terminal Universal Interconnection Networks Using Contact Switches.
IEICE Trans. Inf. Syst., 2021
IEICE Trans. Inf. Syst., 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
Improvement in the Quality of Solutions of a Heuristic Linear Decomposer for Index Generation Functions.
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
On the Minimization of Variables to Represent Partially Defined Classification Functions.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
2019
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79911-2, 2019
On a Minimization of Variables to Represent Sparse Multi-Valued Input Decision Functions.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
A Dynamic Programming Based Method for Optimum Linear Decomposition of Index Generation Functions.
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya.
Proceedings of the Computer Aided Systems Theory - EUROCAST 2019, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
An Exact Optimization Method using ZDDs for Linear Decomposition of Symmetric Index Generation Functions.
FLAP, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
An Exact Optimization Method Using ZDDs for Linear Decomposition of Index Generation Functions.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
A High-speed Low-power Deep Neural Network on an FPGA based on the Nested RNS: Applied to an Object Detector.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the Advanced Logic Synthesis, 2018
2017
A Linear Decomposition of Index Generation Functions: Optimization Using Autocorrelation Functions.
J. Multiple Valued Log. Soft Comput., 2017
IEICE Trans. Inf. Syst., 2017
A Balanced Decision Tree Based Heuristic for Linear Decomposition of Index Generation Functions.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
An Exact Optimization Algorithm for Linear Decomposition of Index Generation Functions.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
An algorithm to find optimum support-reducing decompositions for index generation functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
An FFT Circuit for a Spectrometer of a Radio Telescope using the Nested RNS including the Constant Division.
SIGARCH Comput. Archit. News, 2016
An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (<i>k</i>).
J. Multiple Valued Log. Soft Comput., 2016
LUT Cascades Based on Edge-Valued Multi-Valued Decision Diagrams: Application to Packet Classification.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016
2015
ACM Trans. Reconfigurable Technol. Syst., 2015
IEICE Trans. Inf. Syst., 2015
A Reduction Method for the Number of Variables to Represent Index Generation Functions: s-Min Method.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79870-2, 2014
A Heterogeneous Multi-valued Decision Diagram Machine for Encoded Characteristic Function for Non-zero Outputs.
J. Multiple Valued Log. Soft Comput., 2014
Piecewise Arithmetic Expressions of Numeric Functions and Their Application to Design of Numeric Function Generators.
J. Multiple Valued Log. Soft Comput., 2014
EVMDD-Based Analysis and Diagnosis Methods of Multi-State Systems with Multi-State Components.
J. Multiple Valued Log. Soft Comput., 2014
IET Comput. Digit. Tech., 2014
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
A Method to Find Linear Decompositions for Incompletely Specified Index Generation Functions Using Difference Matrix.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
IEICE Trans. Inf. Syst., 2014
IEICE Trans. Inf. Syst., 2014
A Lower Bound on the Number of Variables to Represent Incompletely Specified Index Generation Functions.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Analysis Methods of Multi-state Systems Partially Having Dependent Components Using Multiple-Valued Decision Diagrams.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Multiple-Valued Index Generation Functions: Reduction of Variables by Linear Transformation.
J. Multiple Valued Log. Soft Comput., 2013
IEICE Trans. Inf. Syst., 2013
IEICE Trans. Inf. Syst., 2013
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
An Application of Autocorrelation Functions to Find Linear Decompositions for Incompletely Specified Index Generation Functions.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
A Machine to Evaluate Decomposed Multi-Terminal Multi-Valued Decision Diagrams for Characteristic Functions.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Minimization of the Number of Edges in an EVMDD by Variable Grouping for Fast Analysis of Multi-State Systems.
Proceedings of the 43rd IEEE International Symposium on Multiple-Valued Logic, 2013
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013
2012
SIGARCH Comput. Archit. News, 2012
J. Multiple Valued Log. Soft Comput., 2012
A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.
Microprocess. Microsystems, 2012
A Design Method of a Regular Expression Matching Circuit Based on Decomposed Automaton.
IEICE Trans. Inf. Syst., 2012
A Fast Head-Tail Expression Generator for TCAM - Application to Packet Classification.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Multiple-Valued Input Index Generation Functions: Optimization by Linear Transformation.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Multi-terminal Multi-valued Decision Diagrams for Characteristic Function Representing Cluster Decomposition.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
On a Wideband Fast Fourier Transform Using Piecewise Linear Approximations: Application to a Radio Telescope Spectrometer.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
A Low-Cost and High-Performance Virus Scanning Engine Using a Binary CAM Emulator and an MPU.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2011
J. Comput. Appl. Math., 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
A Comparison of Heterogeneous Multi-valued Decision Diagram Machines for Multiple-Output Logic Functions.
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 41st IEEE International Symposium on Multiple-Valued Logic, 2011
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
2010
J. Comput. Appl. Math., 2010
Programmable Architectures and Design Methods for Two-Variable Numeric Function Generators.
IPSJ Trans. Syst. LSI Des. Methodol., 2010
IEICE Trans. Inf. Syst., 2010
A Parallel Branching Program Machine for Sequential Circuits: Implementation and Evaluation.
IEICE Trans. Inf. Syst., 2010
A Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.
IEICE Trans. Inf. Syst., 2010
Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010
On the Number of Products to Represent Interval Functions by SOPs with Four-Valued Variables.
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
Proceedings of the 40th IEEE International Symposium on Multiple-Valued Logic, 2010
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79812-2, 2009
IEEE Trans. Computers, 2009
Proceedings of the ISMVL 2009, 2009
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions.
Proceedings of the ISMVL 2009, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators.
Proceedings of the 38th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2008), 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Proceedings of the FPL 2008, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
J. Multiple Valued Log. Soft Comput., 2007
Design Method for Numerical Function Generators Using Recursive Segmentation and EVBDDs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
BDD Representation for Incompletely Specified Multiple-Output Logic Functions and Its Applications to the Design of LUT Cascades.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
IEICE Trans. Inf. Syst., 2007
A New Equivalence Relation of Logic Functions and Its Application in the Design of AND-OR-EXOR Networks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Design Method for Numerical Function Generators Based on Polynomial Approximation for FPGA Implementation.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
A Design of AES Encryption Circuit with 128-bit Keys Using Look-Up Table Ring on FPGA.
IEICE Trans. Inf. Syst., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Compact Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Efficient Computation of Canonical Form under Variable Permutation and Negation for Boolean Matching in Large Libraries.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 36th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), 2006
Proceedings of the 15th Asian Test Symposium, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Multiple Valued Log. Soft Comput., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Output Phase Optimization for AND-OR-EXOR PLAs with Decoders and Its Application to Design of Adders.
IEICE Trans. Inf. Syst., 2005
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Hahoe KAIST Robot Theatre: Learning Rules of Interactive Robot Behavior as a Multiple-Valued Logic Synthesis Problem.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.
Proceedings of the 42nd Design Automation Conference, 2005
2004
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades.
Proceedings of the 34th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2004), 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003
Cascade Realizations of Two-valued Input Multiple-Valued Output Functions using Decomposition of Group Functions.
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 33rd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2003), 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Comparison of Decision Diagrams for Multiple-Output Logic Functions.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002
2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Compact SOP Representations for Multiple-Output Functions: An Encoding Method Using Multiple-Valued Logic.
Proceedings of the 31st IEEE International Symposium on Multiple-Valued Logic, 2001
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001
Proceedings of ASP-DAC 2001, 2001
2000
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000
On the Number of Dependent Variables for Incompletely Specified Multiple-Valued Functions.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams.
Proceedings of the 30th IEEE International Symposium on Multiple-Valued Logic, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
Exact minimization of fixed polarity Reed-Muller expressions for incompletely specified functions.
Proceedings of ASP-DAC 2000, 2000
1999
Totally Undecomposable Functions: Applications to Efficient Multiple-Valued Decompositions.
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Proceedings of the 29th IEEE International Symposium on Multiple-Valued Logic, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
On the Properties of Multiple-Valued Functions that are Symmetric in both Variable Values and Labels.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams.
Proceedings of the 28th IEEE International Symposium on Multiple-Valued Logic, 1998
Proceedings of the ASP-DAC '98, 1998
Proceedings of the ASP-DAC '98, 1998
1997
IEEE Trans. Computers, 1997
Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions.
IEEE Trans. Computers, 1997
Comparison of the Worst and Best Sum-of-Products Expressions for Multiple-Valued Functions.
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Proceedings of the 27th IEEE International Symposium on Multiple-Valued Logic, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Syst. Comput. Jpn., 1996
A Method to Represent Multiple-Output Switching Functions by Using Multi-Valued Decision Diagrams.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996
1995
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995
Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995
1994
Calculation of Reed-Muller-Fourier Coefficients of Multiple-Valued Functions through Multiple-Place Decision Diagrams.
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994
1993
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
IEEE Trans. Computers, 1993
1992
Syst. Comput. Jpn., 1992
Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision Diagrams.
Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992
1991
Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.
IEEE Trans. Computers, 1991
A Transformation of Multiple-Valued Input Two-Valued Output Functions and its Application to Simplification of Exclusive-or Sum-of-Products Expressions.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, 1991
1990
EXMIN: A Simplification Algorithm for Exclusive-OR-Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions.
Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990
1989
1988
1986
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986
1985
An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs.
IEEE Trans. Computers, 1985
1984
IEEE Trans. Computers, 1984
1981
Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays.
IEEE Trans. Computers, 1981
1979
IEEE Trans. Computers, 1979
1978
IEEE Trans. Computers, 1978
IEEE Trans. Computers, 1978
Proceedings of the eighth international symposium on Multiple-valued logic, 1978
1976
1975