Lanlan Cui

According to our database, Lanlan Cui authored at least 4 papers between 2019 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision.

Lanlan Cui, Fei Wu, Xiaojian Liu, Meng Zhang, Renzhi Xiao, Changsheng Xie

ACM Trans. Design Autom. Electr. Syst., 2022

A Low Bit-Width LDPC Min-Sum Decoding Scheme for NAND Flash.

Lanlan Cui, Xiaojian Liu, Fei Wu, Zhonghai Lu, Changsheng Xie

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020

BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash Memory.

Meng Zhang, Fei Wu, Qin Yu, Weihua Liu, Lanlan Cui, Yahui Zhao, Changsheng Xie

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

VaLLR: Threshold Voltage Distribution Aware LLR Optimization to Improve LDPC Decoding Performance for 3D TLC NAND Flash.

Lanlan Cui, Fei Wu, Xiaojian Liu, Meng Zhang, Changsheng Xie

Proceedings of the 37th IEEE International Conference on Computer Design, 2019