Larry L. Kinney

According to our database1, Larry L. Kinney authored at least 29 papers between 1968 and 2004.

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Bibliography

2004
Combining dictionary coding and LFSR reseeding for test data compression.
Proceedings of the 41th Design Automation Conference, 2004

2003
Development of Energy Consumption Ratio Test.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Vector Generation Based on Correlation Model for Ratio-Iddq.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

1999
Design of a bus-based shared-memory multiprocessor DICE.
Microprocess. Microsystems, 1999

1996
Global Bus Design of a Bus-Based COMA Multiprocessor DICE.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

1993
Incremental test pattern generation.
Proceedings of the 11th IEEE VLSI Test Symposium (VTS'93), 1993

1992
Relating the Cyclic Behavior of Linear and Intrainverted Feedback Shift Registers.
IEEE Trans. Computers, 1992

1991
Concurrent Error Detection for Restricted Fault Sets in Sequential Circuits and Microprogrammed Control Units Using Convolutional Codes.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Concurrent Error Detection in Sequential Circuits Using Convolutional Codes.
Proceedings of the Applied Algebra, 1991

1990
Integrated Pull Manufacturing: The Integration of MAP and PULL Systems.
Proceedings of the First International Conference on Systems Integration, 1990

1988
Evaluation of a concurrent error detection method for microprogrammed control units.
Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28, 1988

Error Detection with Latency in Sequential Circuits.
Proceedings of the Proceedings International Test Conference 1988, 1988

Distributed Termination on a Mesh.
Proceedings of the International Conference on Parallel Processing, 1988

1986
C-Testability of Two-Dimensional Iterative Arrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Techniques for Testing Hexagonally Connected Systolic Arrays.
Proceedings of the Proceedings International Test Conference 1986, 1986

A Group Probing Strategy for Testing Large Number of Chips.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
Concurrent Fault Detection in Microprogrammed Control Units.
IEEE Trans. Computers, 1985

1984
A High-Performance, Multi-Link, Multi-Protocol Data Link Controller for an Experimental Distributed Computer Testbed.
Proceedings of the 4th International Conference on Distributed Computing Systems, 1984

1982
Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units.
Proceedings of the Proceedings International Test Conference 1982, 1982

1981
Fault Tolerant Distributed Computing with Very High Speed Integrated Circuits.
Proceedings of the IEEE Real-Time Systems Symposium, 1981

An Architecture for a VHSIC Computer.
Proceedings of the 8th Annual Symposium on Computer Architecture, 1981

1978
Analysis of a Multiprocessor System with a Shared Bus.
Proceedings of the 5th Annual Symposium on Computer Architecture, 1978

1972
B72-11 An Introduction to Switching System Design.
IEEE Trans. Computers, 1972

Output Sufficient Modules for Uniform Decomposition of Synchronous Sequential Circuits
Proceedings of the 13th Annual Symposium on Switching and Automata Theory, 1972

A systematic approach to the design of digital bussing structures.
Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '72 Fall Joint Computer Conference, December 5-7, 1972, Anaheim, California, USA, 1972

1971
A Characterization of Some Asynchronous Sequential Networks and State Assignments.
IEEE Trans. Computers, 1971

Serial Adders with Overflow Correction.
IEEE Trans. Computers, 1971

1970
Decomposition of Asynchronous Sequential Switching Circuits.
IEEE Trans. Computers, 1970

1968
A Characterization of Some Asynchronous State Assignments
Proceedings of the 9th Annual Symposium on Switching and Automata Theory, 1968


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