Gyungho Lee

According to our database1, Gyungho Lee authored at least 68 papers between 1985 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
Dynamic reencryption of return addresses.
IET Information Security, 2019

HW-CDI: Hard-Wired Control Data Integrity.
IEEE Access, 2019

2018
Detecting Code Reuse Attacks with Branch Prediction.
IEEE Computer, 2018

2014
Monitoring Translation Lookahead Buffers to Detect Code Injection Attacks.
IEEE Computer, 2014

2012
Special section: Trusting software behavior.
Future Generation Comp. Syst., 2012

A Memory Access Validation Scheme against Payload Injection Attacks.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2012

2010
Erratum to "Access region cache with register guided memory reference partitioning" [Journal of Systems Architecture 55 (2009) 434-445].
Journal of Systems Architecture - Embedded Systems Design, 2010

Micro-Architecture Support for Integrity Measurement on Dynamic Instruction Trace.
J. Information Security, 2010

Prospect of Fine Grain Dynamic Memory Access Control with Profiling.
Proceedings of the Fourth International Conference on Emerging Security Information Systems and Technologies, 2010

Countering code injection attacks with TLB and I/O monitoring.
Proceedings of the 28th International Conference on Computer Design, 2010

2009
Indirect Branch Validation Unit.
Microprocessors and Microsystems - Embedded Hardware Design, 2009

Access region cache with register guided memory reference partitioning.
Journal of Systems Architecture - Embedded Systems Design, 2009

StackLock with simple FSM.
Proceedings of the 2009 IEEE International Conference on Electro/Information Technology, 2009

2007
Augmenting Branch Predictor to Secure Program Execution.
Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2007

An Efficient Hardware Support for Control Data Validation.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Microarchitectural Protection Against Stack-Based Buffer Overflow Attacks.
IEEE Micro, 2006

Architectural Support for Run-Time Validation of Control Flow Transfer.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005
Minimizing the Directory Size for Large-Scale Shared-Memory Multiprocessors.
IEICE Transactions, 2005

Dynamic Partition of Memory Reference Instructions - A Register Guided Approach.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Eliminating Sorting in IP Lookup Devices using Partitioned Table.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Binding Time in Distributed Shared Memories for Generic Patterns of Memory References.
IEICE Transactions, 2004

Run-time Detection of Buffer Overflow Attacks without Explicit Sensor Data Objects.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

Repairing return address stack for buffer overflow protection.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
A scalable multi-porting solution for future wide-issue processors.
Microprocessors and Microsystems, 2003

Run-Time Support for Detection of Memory Access Violations to Prevent Buffer Overflow Exploits.
Proceedings of the Information Security, 6th International Conference, 2003

DDoS attack detection and wavelets.
Proceedings of the 12th International Conference on Computer Communications and Networks, 2003

2002
Encoding Function Pointers and Memory Arrangement Checking against Buffer Overflow Attack.
Proceedings of the Information and Communications Security, 4th International Conference, 2002

2001
A High-Bandwidth Memory Pipeline for Wide Issue Processors.
IEEE Trans. Computers, 2001

Access Region Cache: A Multi-Porting Solution for Future Wide-Issue Processors.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Reducing Cache Pollution of Prefetching in a Small Data Cache.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Alloyed Path-pattern Scheme for Branch Prediction.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Interprocedural Analysis Based on Guarded Array Regions.
Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

2000
A compiler optimization paradigm for dynamic energy management.
SIGARCH Computer Architecture News, 2000

Instruction-level Distributed Microarchitecture Based on Data Decoupling.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

Encoded Program Counter: Self-Protection from Buffer Overflow Attacks.
Proceedings of the International Conference on Internet Computing, 2000

1999
Design of a bus-based shared-memory multiprocessor DICE.
Microprocessors and Microsystems - Embedded Hardware Design, 1999

Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor.
J. Parallel Distrib. Comput., 1999

Access Region Locality for High-Bandwidth Processor Memory System Design.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor.
Proceedings of the 26th Annual International Symposium on Computer Architecture, 1999

1998
On timing constraints of snooping in a bus-based COMA multiprocessor.
Microprocessors and Microsystems - Embedded Hardware Design, 1998

Prospects of distributed shared memory for reducing global traffic in shared-bus multiprocessors.
Journal of Systems Architecture, 1998

Limited Combining Strategies for Large-Scale Shared-Memory Multiprocessors.
J. Parallel Distrib. Comput., 1998

Binding Time in Distributed Shared Memory Architectures.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1997
NN Based ATM Cell Scheduling with Queue Length-Based Priority Scheme.
IEEE Journal on Selected Areas in Communications, 1997

Experience with Efficient Array Data-Flow Analysis for Array Privatization.
Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1997

1996
Global Bus Design of a Bus-Based COMA Multiprocessor DICE.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Relaxing the Inclusion Property in Cache Only Memory Architecture.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

Reducing Coherence Overhead in Shared-Bus Multiprocessors.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
Analysis of Finite Buffered Multistage Combining Networks.
IEEE Trans. Parallel Distrib. Syst., 1995

Parallelizing Iterative Loops with Conditional Branching.
IEEE Trans. Parallel Distrib. Syst., 1995

Symbolic Array Dataflow Analysis for Array Privatization and Program Parallelization.
Proceedings of the Proceedings Supercomputing '95, San Diego, CA, USA, December 4-8, 1995, 1995

Memory Block Relocation in Cache-Only Memory Multiprocessors.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

An assessment of COMA multiprocessors.
Proceedings of IPPS '95, 1995

ATM cell scheduling with queue length-based priority scheme.
Proceedings of the 4th International Conference on Computer Communications and Networks (ICCCN '95), 1995

Intelligent Congestion Control in ATM Networks.
Proceedings of the 5th IEEE Workshop on Future Trends of Distributed Computing Systems (FTDCS 1995), 1995

1994
Omega network-based ATM switch with neural network-controlled bypass queueing and multiplexing.
IEEE Journal on Selected Areas in Communications, 1994

On the Effectiveness of Combining in Resolving "Hot Spot" Contention.
J. Parallel Distrib. Comput., 1994

A High Throughput Packet-Switching Network with Neural Network Controlled Bypass Queueing and Multiplexing.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

1991
A performance bound analysis of multistage combining networks using a probabilistic model.
Proceedings of the 5th international conference on Supercomputing, 1991

Performance of Multistage Combining Networks.
Proceedings of the International Conference on Parallel Processing, 1991

1989
A Performance Bound of Multistage Combining Networks.
IEEE Trans. Computers, 1989

1988
Extra Group Network: A Cost-Effective Fault-Tolerant Multistage Interconnection Network.
Proceedings of the 15th Annual International Symposium on Computer Architecture, 1988

Design and Analysis of A Fault-Tolerant Multistage Interconnection Network for Large-Scale Shared Memory Parallel Computers.
Proceedings of the International Conference on Parallel Processing, 1988

Automatic Restructuring of Conditional Cyclic Loops.
Proceedings of the International Conference on Parallel Processing, 1988

1987
Another Combining Scheme to Reduce Hot Spot Contention in Large Scale Shared Memory Parallel Computers.
Proceedings of the Supercomputing, 1987

1986
The Effectiveness of Combining in Shared Memory Parallel Computer in the Presence of "Hot Spots".
Proceedings of the International Conference on Parallel Processing, 1986

1985
An Empirical Study of Automatic Restructuring of Nonnumerical Programs for Parallel Processors.
IEEE Trans. Computers, 1985

The Effectiveness of Automatic Restructuring on Nonnumerical Programs.
Proceedings of the International Conference on Parallel Processing, 1985


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