Vijay S. Iyengar

According to our database1, Vijay S. Iyengar authored at least 37 papers between 1982 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2008
Event detection in sensor networks for modern oil fields.
Proceedings of the Second International Conference on Distributed Event-Based Systems, 2008

2007
Analytics for Audit and Business Controls in Corporate Travel and Entertainment.
Proceedings of the Data Mining and Analytics 2007, 2007

2006
Evaluation of IT Portfolio Options by Linking to Business Services.
Proceedings of the Data Engineering Issues in E-Commerce and Services, 2006

2004
On detecting space-time clusters.
Proceedings of the Tenth ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2004

2003
Epi-SPIRE: a system for environmental and public health activity monitoring.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

2002
Recommender Systems Using Linear Classifier.
J. Mach. Learn. Res., 2002

Transforming data to satisfy privacy constraints.
Proceedings of the Eighth ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, 2002

2001
Evaluating multiple attribute items using queries.
Proceedings of the Proceedings 3rd ACM Conference on Electronic Commerce (EC-2001), 2001

Empirical Study of Recommender Systems Using Linear Classifiers.
Proceedings of the Knowledge Discovery and Data Mining, 2001

Texture-space segmentation and multi-resolution mapping for forestry applications.
Proceedings of the IEEE International Conference on Acoustics, 2001

2000
Active learning using adaptive resampling.
Proceedings of the sixth ACM SIGKDD international conference on Knowledge discovery and data mining, 2000

1999
HOT: Heuristics for Oblique Trees.
Proceedings of the 11th IEEE International Conference on Tools with Artificial Intelligence, 1999

1996
Representative Traces for Processor Models with Infinite Cache.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

1995
AVPGEN-A test generator for architecture verification.
IEEE Trans. Very Large Scale Integr. Syst., 1995

1994
Identification of redundant delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994

Architectural Verification of Processors Using Symbolic Instruction Graphs.
Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

1992
Optimized test application timing for AC test.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992

A Small Test Generator for Large Designs.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Delay Test: The Next Frontier for LSSD Test Systems.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

AC Test Quality: Beyond Transition Fault Coverage.
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

Constraint Slving for Test Case Generation.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Identification of Single Gate Delay Fault Redundancies.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991
Test Application Timing: The Unexplored Issue in AC Test.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

Symbolic implication in test generation.
Proceedings of the conference on European design automation, 1991

1990
On computing the sizes of detected delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1990

1989
Synthesis of Pseudo-Random Pattern Testable Designs.
Proceedings of the Proceedings International Test Conference 1989, 1989

1988
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. on CAD of Integrated Circuits and Systems, 1988

Timing Analysis Using Functional Analysis.
IEEE Trans. Computers, 1988

Delay Test Generation 2: Algebra and Algorithms.
Proceedings of the Proceedings International Test Conference 1988, 1988

Delay Test Generation 1: Concepts and Coverage Metrics.
Proceedings of the Proceedings International Test Conference 1988, 1988

On simulating faults in parallel.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1986
Transition Fault Simulation by Parallel Pattern Single Fault Propagation.
Proceedings of the Proceedings International Test Conference 1986, 1986

Efficient Fault Simulation of CMOS Circuits with Accurate Models.
Proceedings of the Proceedings International Test Conference 1986, 1986

SLS - a fast switch level simulator for verification and fault coverage analysis.
Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985
Concurrent Fault Detection in Microprogrammed Control Units.
IEEE Trans. Computers, 1985

Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.
Proceedings of the Proceedings International Test Conference 1985, 1985

1982
Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units.
Proceedings of the Proceedings International Test Conference 1982, 1982


  Loading...