Farid N. Najm

According to our database1, Farid N. Najm authored at least 138 papers between 1988 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to estimation and modeling of power dissipation in integrated circuits.".

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2019
Power Scheduling With Active RC Power Grids.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Efficient Simulation of Electromigration Damage in Large Chip Power Grids Using Accurate Physical Models (Invited Paper).
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Power Grid Fixing for Electromigration-induced Voltage Failures.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Power Grid Electromigration Checking Using Physics-Based Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
Generating Current Constraints to Guarantee RLC Power Grid Safety.
ACM Trans. Design Autom. Electr. Syst., 2017

Fast Vectorless RLC Grid Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Parallel Simulation-Based Verification of RC Power Grids.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Power scheduling with active power grids.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Power grid verification under transient constraints.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Fast physics-based electromigration assessment by efficient solution of linear time-invariant (LTI) systems.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Verification of the Power and Ground Grids Under General and Hierarchical Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Generating Current Budgets to Guarantee Power Grid Safety.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Generating voltage drop aware current budgets for RC power grids.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A fast layer elimination approach for power grid reduction.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Fast physics-based electromigration checking for on-die power grids.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Accurate verification of RC power grids.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Fast simulation-based verification of RC power grids.
Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

2015
Redundancy-Aware Power Grid Electromigration Checking Under Workload Uncertainties.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Physical Design Challenges in the Chip Power Distribution Network.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Generating circuit current constraints to guarantee power grid safety.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2013
A vectorless framework for power grid electromigration checking.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

Redundancy-aware electromigration checking for mesh power grids.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Overview of vectorless/early power grid verification.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Incremental power grid verification.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Fast Vectorless Power Grid Verification Under an RLC Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Efficient RC power grid verification using node elimination.
Proceedings of the Design, Automation and Test in Europe, 2011

A fast approach for static timing analysis covering all PVT corners.
Proceedings of the 48th Design Automation Conference, 2011

Power grid correction using sensitivity analysis under an RC model.
Proceedings of the 48th Design Automation Conference, 2011

Power grid verification using node and branch dominance.
Proceedings of the 48th Design Automation Conference, 2011

2010
Verification and Codesign of the Package and Die Power Delivery System Using Wavelets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Power grid correction using sensitivity analysis.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Early P/G grid voltage integrity verification.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Managing verification error traces with bounded model debugging.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Low-Power Programmable FPGA Routing Circuitry.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Full-Chip Model for Leakage-Current Estimation Considering Within-Die Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

PSTA-based branch and bound approach to the silicon speedpath isolation problem.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Quantifying robustness metrics in parameterized static timing analysis.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Clock skew optimization via wiresizing for timing sign-off covering all process corners.
Proceedings of the 46th Design Automation Conference, 2009

Fast vectorless power grid verification using an approximate inverse technique.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Parameterized timing analysis with general delay models and arbitrary variation sources.
Proceedings of the 45th Design Automation Conference, 2008

2007
Variations-Aware Low-Power Design and Block Clustering With Voltage Scaling.
IEEE Trans. Very Large Scale Integr. Syst., 2007

A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Early power grid verification under circuit current uncertainties.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

A geometric approach for early power grid verification using current constraints.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Maximum circuit activity estimation using pseudo-boolean satisfiability.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation.
Proceedings of the 44th Design Automation Conference, 2007

2006
Dynamic-range estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Voltage-Aware Static Timing Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis and verification of power grids considering process-induced leakage-current variations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

High-level current macro model for logic blocks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Active leakage power optimization for FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Handling inductance in early power grid verification.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

An adaptive FPGA architecture with process variation compensation and reduced leakage.
Proceedings of the 43rd Design Automation Conference, 2006

A family of cells to reduce the soft-error-rate in ternary-CAM.
Proceedings of the 43rd Design Automation Conference, 2006

A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
A Case for Asymmetric-Cell Cache Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Early power estimation for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Power grid voltage integrity verification.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Incremental partitioning-based vectorless power grid verification.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Statistical timing analysis with two-sided constraints.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A non-parametric approach for dynamic range estimation of nonlinear systems.
Proceedings of the 42nd Design Automation Conference, 2005

On the need for statistical timing analysis.
Proceedings of the 42nd Design Automation Conference, 2005

Variations-aware low-power design with voltage scaling.
Proceedings of the 42nd Design Automation Conference, 2005

Look-up table leakage reduction for FPGAs.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Leakage power: trends, analysis and avoidance.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Power estimation techniques for FPGAs.
IEEE Trans. Very Large Scale Integr. Syst., 2004

An Asymmetric SRAM Cell to Lower Gate Leakage.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Dynamic range estimation for nonlinear systems.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Low-power programmable routing circuitry for FPGAs.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Active leakage power optimization for FPGAs.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

An analytical approach for dynamic range estimation.
Proceedings of the 41th Design Automation Conference, 2004

Statistical timing analysis based on a timing yield model.
Proceedings of the 41th Design Automation Conference, 2004

Worst-case circuit delay taking into account power supply variations.
Proceedings of the 41th Design Automation Conference, 2004

A novel low-power FPGA routing switch.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Interconnect capacitance estimation for FPGAs.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Energy and peak-current per-cycle estimation at RTL.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Low-leakage asymmetric-cell SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2003

Switching activity analysis and pre-layout activity prediction for FPGAs.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Design Techniques for Gate-Leakage Reduction in CMOS Circuits.
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

ESTIMA: an architectural-level power estimator for multi-ported pipelined register files.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Statistical Verification of Power Grids Considering Process-Induced Leakage Current Variations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Timing Analysis in Presence of Power Supply and Ground Voltage Variations.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A static pattern-independent technique for power grid voltage integrity verification.
Proceedings of the 40th Design Automation Conference, 2003

Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations.
Proceedings of the 40th Design Automation Conference, 2003

2002
A technique for Improving dual-output domino logic.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Estimation of state line statistics in sequential circuits.
ACM Trans. Design Autom. Electr. Syst., 2002

A multigrid-like technique for power grid analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

High-level area estimation.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Power-aware technology mapping for LUT-based FPGAs.
Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

High-level current macro-model for power-grid analysis.
Proceedings of the 39th Design Automation Conference, 2002

2001
Power estimation for large sequential circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Prelayout estimation of individual wire lengths.
IEEE Trans. Very Large Scale Integr. Syst., 2001

Frequency-domain supply current macro-model.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

2000
Power modeling for high-level power estimation.
IEEE Trans. Very Large Scale Integr. Syst., 2000

Analytical models for RTL power estimation of combinational andsequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Pre-layout estimation of individual wire lengths.
Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

A Statistical Model for Electromigration Failures.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

High-level power estimation with interconnect effects.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

1999
High-level area and power estimation for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

An optimization technique for dual-output domino logic.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Energy-per-cycle estimation at RTL.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Power macro-models for DSP blocks with application to high-level synthesis.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

1998
Post-Mapping Transformations for Low-Power Synthesis.
VLSI Design, 1998

Guest Editorial.
VLSI Design, 1998

Statistical Estimation of the , Switching Activity in VLSI Circuits.
VLSI Design, 1998

Delay Estimation VLSI Circuits from a High-Level View.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Accurate power estimation for large sequential circuits.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Monte-Carlo approach for power estimation in sequential circuits.
Proceedings of the European Design and Test Conference, 1997

Technology-Dependent Transformations for Low-Power Synthesis.
Proceedings of the 34st Conference on Design Automation, 1997

Power Macromodeling for High Level Power Estimation.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Towards a high-level power estimation capability [digital ICs].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

High-level power estimation and the area complexity of Boolean functions.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Towards a high-level power estimation capability.
Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

Power estimation techniques for integrated circuits.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Extreme Delay Sensitivity and the Worst-Case Switching Activity in VLSI Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Power Estimation in Sequential Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

Feedback, Correlation, and Delay Concerns in the Power Estimation of VLSI Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A survey of power estimation techniques in VLSI circuits.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Low-pass filter for computing the transition density in digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Statistical Estimation of the Switching Activity in Digital Circuits.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A Monte Carlo approach for power estimation.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Transition density: a new measure of activity in digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
McPOWER: a Monte Carlo approach to power estimation.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Maximum Current Estimation in CMOS Circuits.
Proceedings of the 29th Design Automation Conference, 1992

1991
An extension of probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Transition Density, A Stochastic Measure of Activity in Digital Circuits.
Proceedings of the 28th Design Automation Conference, 1991

1990
The complexity of fault detection in MOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Probabilistic simulation for reliability analysis of CMOS VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

1989
Computation of bus current variance for reliability estimation of VLSI circuits.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988
CREST-a current estimator for CMOS circuits.
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Pattern-Independent Current Estimation for Reliability Analysis of CMOS Circuits.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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