Laura Carrington

According to our database1, Laura Carrington authored at least 51 papers between 2002 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
Performance Evaluation of Scale-Free Graph Algorithms in Low Latency Non-volatile Memory.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

2016
PMaC's green queue: a framework for selecting energy optimal DVFS configurations in large scale MPI applications.
Concurrency and Computation: Practice and Experience, 2016

The case for colocation of high performance computing workloads.
Concurrency and Computation: Practice and Experience, 2016

AutoMOMML: Automatic Multi-objective Modeling with Machine Learning.
Proceedings of the High Performance Computing - 31st International Conference, 2016

Characterization and bottleneck analysis of a 64-bit ARMv8 platform.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

ADAMANT: Tools to Capture, Analyze, and Manage Data Movement.
Proceedings of the International Conference on Computational Science 2016, 2016

2015
PEBIL: binary instrumentation for practical data-intensive program analysis.
Cluster Computing, 2015

Optimizing codes on the Xeon Phi: a case-study with LAMMPS.
Proceedings of the 2015 XSEDE Conference: Scientific Advancements Enabled by Enhanced Cyberinfrastructure, St. Louis, MO, USA, July 26, 2015

Performance and energy efficiency analysis of 64-bit ARM using GAMESS.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015

Compute bottlenecks on the new 64-bit ARM.
Proceedings of the 3rd International Workshop on Energy Efficient Supercomputing, 2015

Tuning tasks, granularity, and scratchpad size for energy efficiency.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015

Performance and energy-efficiency analysis of ARM processors for HPC workloads.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015

Predicting Optimal Power Allocation for CPU and DRAM Domains.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

Building Blocks for a System-Wide Power and Thermal Management Framework.
Proceedings of the 21st IEEE International Conference on Parallel and Distributed Systems, 2015

VecMeter: Measuring Vectorization on the Xeon Phi.
Proceedings of the 2015 IEEE International Conference on Cluster Computing, 2015

2014
Making the Most of SMT in HPC: System- and Application-Level Perspectives.
TACO, 2014

Enabling fair pricing on high performance computer systems with node sharing.
Scientific Programming, 2014

An evaluation of threaded models for a classical MD proxy application.
Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014

A caching approach to reduce communication in graph search algorithms.
Proceedings of the 2014 International Workshop on Data Intensive Scalable Computing Systems, 2014

Modeling the Impact of Reduced Memory Bandwidth on HPC Applications.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Characterizing the Performance-Energy Tradeoff of Small ARM Cores in HPC Computation.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Evaluation of emerging memory technologies for HPC, data intensive applications.
Proceedings of the 2014 IEEE International Conference on Cluster Computing, 2014

Efficient speed (ES): Adaptive DVFS and clock modulation for energy efficiency.
Proceedings of the 2014 IEEE International Conference on Cluster Computing, 2014

2013
Characterizing Large-Scale HPC Applications through Trace extrapolation.
Parallel Processing Letters, 2013

Toward application-specific memory reconfiguration for energy efficiency.
Proceedings of the 1st International Workshop on Energy Efficient Supercomputing, 2013

Enabling fair pricing on HPC systems with node sharing.
Proceedings of the International Conference for High Performance Computing, 2013

Inferring Large-Scale Computation Behavior via Trace Extrapolation.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Understanding the performance of stencil computations on Intel's Xeon Phi.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

2012
Efficient HPC Data Motion via Scratchpad Memory.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A Static Binary Instrumentation Threading Model for Fast Memory Trace Collection.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Modeling Power and Energy Usage of HPC Kernels.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Modeling and Predicting Performance of High Performance Computing Applications on Hardware Accelerators.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Green Queue: Customized Large-Scale Clock Frequency Scaling.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

2011
A tool for characterizing and succinctly representing the data access patterns of applications.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

Modeling and predicting application performance on hardware accelerators.
Proceedings of the 2011 IEEE International Symposium on Workload Characterization, 2011

An idiom-finding tool for increasing productivity of accelerators.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Auto-tuning for Energy Usage in Scientific Applications.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
PEBIL: Efficient static binary instrumentation for Linux.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

PIR: PMaC's Idiom Recognizer.
Proceedings of the 39th International Conference on Parallel Processing, 2010

2009
PSnAP: Accurate Synthetic Address Streams through Memory Profiles.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

PSINS: An Open Source Event Tracer and Execution Simulator for MPI Applications.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
DARPA's HPCS Program- History, Models, Tools, Languages.
Advances in Computers, 2008

Performance Prediction and Ranking of Supercomputers.
Advances in Computers, 2008

High-frequency simulations of global seismic wave propagation using SPECFEM3D_GLOBE on 62K processors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

2007
A genetic algorithms approach to modeling the performance of memory-bound computations.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

2006
A performance prediction framework for scientific applications.
Future Generation Comp. Syst., 2006

2005
How Well Can Simple Metrics Represent the Performance of HPC Applications?
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

2003
Performance Modeling of HPC Applications.
Proceedings of the Parallel Computing: Software Technology, 2003

A Performance Prediction Framework for Scientific Applications.
Proceedings of the Computational Science - ICCS 2003, 2003

2002
A framework for performance modeling and prediction.
Proceedings of the 2002 ACM/IEEE conference on Supercomputing, 2002


  Loading...