Michael Laurenzano

According to our database1, Michael Laurenzano authored at least 47 papers between 2005 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Caliper: Interference Estimator for Multi-tenant Environments Sharing Architectural Resources.
TACO, 2019

Outlier Detection for Improved Data Quality and Diversity in Dialog Systems.
Proceedings of the 2019 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, 2019

An Evaluation Dataset for Intent Classification and Out-of-Scope Prediction.
Proceedings of the 2019 Conference on Empirical Methods in Natural Language Processing and the 9th International Joint Conference on Natural Language Processing, 2019

2018
Rethinking Numerical Representations for Deep Neural Networks.
CoRR, 2018

Proctor: Detecting and Investigating Interference in Shared Datacenters.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Architectural support for convolutional neural networks on modern CPUs.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018

2017
Reining in Long Tails in Warehouse-Scale Computers with Quick Voltage Boosting Using Adrenaline.
ACM Trans. Comput. Syst., 2017

DeftNN: addressing bottlenecks for DNN execution on GPUs via synapse vector elimination and near-compute data fission.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

2016
Designing Future Warehouse-Scale Computers for Sirius, an End-to-End Voice and Vision Personal Assistant.
ACM Trans. Comput. Syst., 2016

Sirius Implications for Future Warehouse-Scale Computers.
IEEE Micro, 2016

PMaC's green queue: a framework for selecting energy optimal DVFS configurations in large scale MPI applications.
Concurrency and Computation: Practice and Experience, 2016

The case for colocation of high performance computing workloads.
Concurrency and Computation: Practice and Experience, 2016

Input responsiveness: using canary inputs to dynamically steer approximation.
Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2016

CrystalBall: Statically analyzing runtime behavior via deep sequence learning.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Continuous shape shifting: Enabling loop co-optimization via near-free dynamic code rewriting.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Concise loads and stores: The case for an asymmetric compute-memory architecture for approximation.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Characterization and bottleneck analysis of a 64-bit ARMv8 platform.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

PowerChop: Identifying and Managing Non-critical Units in Hybrid Processor Architectures.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Lightweight, Early Identification of At-Risk CS1 Students.
Proceedings of the 2016 ACM Conference on International Computing Education Research, 2016

2015
PEBIL: binary instrumentation for practical data-intensive program analysis.
Cluster Computing, 2015

Performance and energy efficiency analysis of 64-bit ARM using GAMESS.
Proceedings of the 2nd International Workshop on Hardware-Software Co-Design for High Performance Computing, 2015

Compute bottlenecks on the new 64-bit ARM.
Proceedings of the 3rd International Workshop on Energy Efficient Supercomputing, 2015

DjiNN and Tonic: DNN as a service and its implications for future warehouse scale computers.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Octopus-Man: QoS-driven task management for heterogeneous multicores in warehouse-scale computers.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Sirius: An Open End-to-End Voice and Vision Personal Assistant and Its Implications for Future Warehouse Scale Computers.
Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, 2015

AREP: Adaptive Resource Efficient Prefetching for Maximizing Multicore Performance.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Making the Most of SMT in HPC: System- and Application-Level Perspectives.
TACO, 2014

SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Protean Code: Achieving Near-Free Online Code Transformations for Warehouse Scale Computers.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Modeling the Impact of Reduced Memory Bandwidth on HPC Applications.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Characterizing the Performance-Energy Tradeoff of Small ARM Cores in HPC Computation.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

2013
Characterizing Large-Scale HPC Applications through Trace extrapolation.
Parallel Processing Letters, 2013

Inferring Large-Scale Computation Behavior via Trace Extrapolation.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Understanding the performance of stencil computations on Intel's Xeon Phi.
Proceedings of the 2013 IEEE International Conference on Cluster Computing, 2013

2012
Efficient HPC Data Motion via Scratchpad Memory.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

A Static Binary Instrumentation Threading Model for Fast Memory Trace Collection.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012

Modeling Power and Energy Usage of HPC Kernels.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Green Queue: Customized Large-Scale Clock Frequency Scaling.
Proceedings of the 2012 Second International Conference on Cloud and Green Computing, 2012

2011
An idiom-finding tool for increasing productivity of accelerators.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Auto-tuning for Energy Usage in Scientific Applications.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

Reducing Energy Usage with Memory and Computation-Aware Dynamic Frequency Scaling.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
PEBIL: Efficient static binary instrumentation for Linux.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

2009
PSINS: An Open Source Event Tracer and Execution Simulator for MPI Applications.
Proceedings of the Euro-Par 2009 Parallel Processing, 2009

2008
High-frequency simulations of global seismic wave propagation using SPECFEM3D_GLOBE on 62K processors.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

2005
Low cost trace-driven memory simulation using SimPoint.
SIGARCH Computer Architecture News, 2005

How Well Can Simple Metrics Represent the Performance of HPC Applications?
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005


  Loading...