Leonard F. Register

Affiliations:

University of Texas at Austin, Microelectronics Research Center, TX, USA

According to our database¹, Leonard F. Register authored at least 6 papers between 1998 and 2021.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Awards

IEEE Fellow

IEEE Fellow 2016, "For contributions to modeling of charge transport in nanoscale CMOS devices".

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2021

2019

Tunnel Barrier Thickness, Interlayer Rotational Alignment, and Top Gating Effects on ReS2/hBN/ReS2 Resonant Interlayer Tunnel Field Effect Transistors.

[BibT_eX]

[DOI]

Omar B. Mohammed

Leonard F. Register

Sanjay K. Banerjee

Proceedings of the Device Research Conference, 2019

2010

Graphene for CMOS and Beyond CMOS Applications.

[BibT_eX]

[DOI]

Sanjay K. Banerjee

Leonard Franklin Register

Proc. IEEE, 2010

2001

Impact of Scaling on CMOS Chip Failure Rate, and Design Rules for Hot Carrier Reliability.

[BibT_eX]

[DOI]

VLSI Design, 2001

1998

Simulation of Optical Excitation to and Emission from Electron Fabry-Perot States Subject to Strong Inelastic Scattering.

[BibT_eX]

[DOI]

Leonard F. Register

VLSI Design, 1998

Theory and Modeling of Lasing Modes in Vertical Cavity Surface Emitting Lasers.

[BibT_eX]

[DOI]

VLSI Design, 1998

Leonard F. Register

Awards

IEEE Fellow

Timeline

Legend:

Links

Online presence:

On csauthors.net:

Bibliography

Loading...