Subhendu Roy

Orcid: 0000-0001-8554-563X

According to our database1, Subhendu Roy authored at least 17 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2022
High-Speed Adder Design Space Exploration via Graph Neural Processes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Machine Learning for Statistical Modeling: The Case of Perpendicular Spin-Transfer-Torque Random Access Memory.
ACM Trans. Design Autom. Electr. Syst., 2021

2019
Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
SD-PUF: Spliced Digital Physical Unclonable Function.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017
A learning bridge from architectural synthesis to physical design for exploring power efficient high-performance adders.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

2016
OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Design for manufacturability and reliability in extreme-scaling VLSI.
Sci. China Inf. Sci., 2016

LRR-DPUF: learning resilient and reliable digital physical unclonable function.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Triple Patterning Lithography (TPL) Layout Decomposition using End-Cutting (JM3 Special Session).
CoRR, 2014

Reliability Aware Gate Sizing Combating NBTI and Oxide Breakdown.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2010
Large Scale VLSI Circuit Simulation Using Point Relaxation.
Proceedings of the 2010 International Conference on Scientific Computing, 2010


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