Liang-Hsin Chen

According to our database, Liang-Hsin Chen authored at least 2 papers between 2012 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A 6.7 MHz to 1.24 GHz 0.0318 mm ² Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen

IEEE J. Solid State Circuits, 2016

2012

A 6.7MHz-to-1.24GHz 0.0318mm² fast-locking all-digital DLL in 90nm CMOS.

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012