Min-Han Hsieh

According to our database, Min-Han Hsieh authored at least 12 papers between 2011 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2016

A 6.7 MHz to 1.24 GHz 0.0318 mm ² Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen

IEEE J. Solid State Circuits, 2016

2015

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.

Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme.

Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013

A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology.

Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS.

Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

System-impact analysis of a large-scale offshore wind farm connected to Taiwan power system.

Li Wang, Chun-Jui Yeh, Min-Han Hsieh, Cheng-Tai Wu, Chieh-Lung Lu

Proceedings of the 2013 IEEE Industry Applications Society Annual Meeting, 2013

2012

An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.

Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 6.7MHz-to-1.24GHz 0.0318mm² fast-locking all-digital DLL in 90nm CMOS.

Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm.

Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

A 12 Gb/s chip-to-chip AC coupled transceiver.

Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.

Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An at-speed self-testable technique for the high speed domino adder.

Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011