Min-Han Hsieh

According to our database1, Min-Han Hsieh authored at least 12 papers between 2011 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2016
A 6.7 MHz to 1.24 GHz 0.0318 mm <sup>2</sup> Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.
IEEE J. Solid State Circuits, 2016

2015
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

System-impact analysis of a large-scale offshore wind farm connected to Taiwan power system.
Proceedings of the 2013 IEEE Industry Applications Society Annual Meeting, 2013

2012
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 6.7MHz-to-1.24GHz 0.0318mm<sup>2</sup> fast-locking all-digital DLL in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A 12 Gb/s chip-to-chip AC coupled transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An at-speed self-testable technique for the high speed domino adder.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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