Lowry P.-T. Wang

According to our database, Lowry P.-T. Wang authored at least 6 papers between 2022 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

DN-FF: A SEU-Tolerant Flip-Flop Design for Advanced Technology Nodes.

Lowry P.-T. Wang, Charles H.-P. Wen

IEEE Trans. Very Large Scale Integr. Syst., March, 2026

2025

Designing Radiation-Hardened D Flip-Flop with Reduced Latency and Area Using Filtering Buffer.

Nelson M.-C. Wu, Lowry P.-T. Wang, Chia-Wei Liang, Charles H.-P. Wen, Herming Chiueh

Proceedings of the 43rd IEEE VLSI Test Symposium, 2025

2024

Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics.

Ralf E.-H. Yee, Nicholas Y.-J. Su, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh

Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

LESER-2: Detailed Consideration in Latch Design under Process Migration for Prevention of Single-Event Double-Node Upsets.

Alan S.-M. Liu, Lowry P.-T. Wang, Charles H.-P. Wen, Herming Chiueh

Proceedings of the IEEE International Test Conference, 2024

2023

Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs.

Sam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen, Herming Chiueh

Proceedings of the IEEE International Test Conference, 2023

2022

Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies.

Sam M.-H. Hsiao, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen

Proceedings of the IEEE International Test Conference, 2022