Charles H.-P. Wen

Orcid: 0000-0003-4623-9941

Affiliations:
  • National Chiao Tung University, Department of Electrical and Computer Engineering, Hsinchu, Taiwan


According to our database1, Charles H.-P. Wen authored at least 95 papers between 2005 and 2024.

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Bibliography

2024
PS-IPS: Deploying Intrusion Prevention System with machine learning on programmable switch.
Future Gener. Comput. Syst., March, 2024

Assessing the impact of communication delays for Autonomous Intersection Management systems.
Veh. Commun., 2024

Temperature-Insensitive Soft-Error-Tolerant Flip-Flop Design For Automotive Electronics.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024

2023
Hierarchical Cooperation and Load Balancing for Scalable Autonomous Vehicle Routing in Multi-Access Edge Computing Environment.
IEEE Trans. Veh. Technol., June, 2023

Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs.
Proceedings of the IEEE International Test Conference, 2023

2022
A General and Automatic Cell Layout Generation Framework With Implicit Learning on Design Rules.
IEEE Trans. Very Large Scale Integr. Syst., 2022

Roadrunner+: An Autonomous Intersection Management Cooperating with Connected Autonomous Vehicles and Pedestrians with Spillback Considered.
ACM Trans. Cyber Phys. Syst., 2022

Rad-Hard Designs by Automated Latching-Delay Assignment and Time-Borrowable D-Flip-Flop.
IEEE Trans. Computers, 2022

Real-Time In-Network Microburst Mitigation on Programmable Switch.
IEEE Access, 2022

SlewFTA: Functional Timing Analysis Considering Slew Propagation.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

P4SF: A High-Performance Stateful Firewall on Commodity P4-Programmable Switch.
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022

Enabling Malware Detection with Machine Learning on Programmable Switch.
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022

Existence of Single-Event Double-Node Upsets (SEDU) in Radiation-Hardened Latches for Sub-65nm CMOS Technologies.
Proceedings of the IEEE International Test Conference, 2022

Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal Probability.
Proceedings of the IEEE International Test Conference in Asia, 2022

SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability.
ACM Trans. Design Autom. Electr. Syst., 2021

AMSER-FF: Area-Minimized Soft-Error-Recoverable Flip-Flop for Radiation Hardening.
Proceedings of the IEEE International Test Conference in Asia, 2021

Generating Layouts of Standard Cells by Implicit Learning on Design Rules for Advanced Processes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Speeding Up Functional Timing Analysis by Concise Formulation of Timed Characteristic Functions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Radiation-Harden RISC Processor for Micro-Satellites in Standard CMOS.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Roadrunner: Autonomous Intersection Management with Dynamic Lane Assignment.
Proceedings of the 23rd IEEE International Conference on Intelligent Transportation Systems, 2020

SAFCast: Smart Inter-Datacenter Multicast Transfer with Deadline Guarantee by Store-And-Forwarding.
Proceedings of the 39th IEEE Conference on Computer Communications, 2020

Profit-Driven Service-Chain Deployment For EDA Requests On Private Cloud.
Proceedings of the 9th IEEE International Conference on Cloud Networking, 2020

SDPTA: Soft-Delay-aware Pattern-based Timing Analysis and Its Path-Fixing Mechanism.
Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019
Dynamic Switch Migration in Distributed Software-Defined Networks to Achieve Controller Load Balance.
IEEE J. Sel. Areas Commun., 2019

P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings.
IEEE Access, 2019

Parcel-Fit: Low Network-Overhead Service-Chain Deployment for Better Datacenter Performance.
Proceedings of the IEEE Conference on Network Function Virtualization and Software Defined Networks, 2019

In-network Congestion-aware Load Balancing at Transport Layer.
Proceedings of the IEEE Conference on Network Function Virtualization and Software Defined Networks, 2019

FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging.
Proceedings of the IEEE International Test Conference, 2019

2018
Online task scheduler in 3D-MCPs with TADVA.
IET Comput. Digit. Tech., 2018

Accurate performance evaluation of VLSI designs with selected CMOS process parameters.
IET Circuits Devices Syst., 2018

SVM-Based Dynamic Voltage Prediction for Online Thermally Constrained Task Scheduling in 3-D Multicore Processors.
IEEE Embed. Syst. Lett., 2018

Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation.
IEEE Access, 2018

Improving Quality of Experience of Service-Chain Deployment for Multiple Users.
Proceedings of the 26th IEEE/ACM International Symposium on Quality of Service, 2018

Skew-Aware Functional Timing Analysis Against Setup Violation for Post-Layout Validation.
Proceedings of the IEEE International Test Conference in Asia, 2018

2017
An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Deploying QoS-assured service function chains with stochastic prediction models on VNF latency.
Proceedings of the 2017 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2017

Speeding up power verification by merging equivalent power domains in RTL design with UPF.
Proceedings of the International Test Conference in Asia, 2017

SLA-driven Ordered Variable-width Windowing for service-chain deployment in SDN datacenters.
Proceedings of the 2017 International Conference on Information Networking, 2017

Accelerating functional timing analysis with encoding duplication removal and redundant state propagation.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

TVM: Tabular VM migration for reducing hop violations of service chains in cloud datacenters.
Proceedings of the IEEE International Conference on Communications, 2017

Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

FASIC: A Fast-Recovery, Adaptively Spanning In-Band Control Plane in Software-Defined Network.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

2016
Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Reducing network cost of minimal-migration based VM management in cloud datacenters.
Proceedings of the 7th International Conference on the Network of the Future, 2016

ERIC: Economical & reconfigurable hybrid-band control for software-defined datacenter network.
Proceedings of the 2016 International Conference on Information Networking, 2016

Fast-yet-accurate variation-aware current and voltage modelling of radiation-induced transient fault.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Speed binning with high-quality structural patterns from functional timing analysis (FTA).
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Demystifying Iddq Data With Process Variation for Automatic Chip Classification.
IEEE Trans. Very Large Scale Integr. Syst., 2015

A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs.
J. Electron. Test., 2015

Dynamic voltage assignment for thermal-constrained task scheduler on 3D multi-core processors.
Proceedings of the VLSI Design, Automation and Test, 2015

SWF: Segmented Wildcard Forwarding for flow migration in OpenFlow datacenter networks.
Proceedings of the 2015 IEEE International Conference on Communications, 2015

An online thermal-constrained task scheduler for 3D multi-core processors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

TA-FTA: transition-aware functional timing analysis with a four-valued encoding.
Proceedings of the 52nd Annual Design Automation Conference, 2015

NACHOS: Network-aware chains orchestration selection for NFV in SDN datacenter.
Proceedings of the 4th IEEE International Conference on Cloud Networking, 2015

2014
TASSER: A temperature-aware statistical soft-error-rate analysis framework for combinational circuits.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

CASTA: CUDA-Accelerated Static Timing Analysis for VLSI Designs.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

EQVMP: Energy-efficient and QoS-aware virtual machine placement for software defined datacenter networks.
Proceedings of the International Conference on Information Networking 2014, 2014

Flexible Parallelized Empirical Mode Decomposition in CUDA for Hilbert Huang Transform.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Fast Scan-Chain Ordering for 3-D-IC Designs Under Through-Silicon-Via (TSV) Constraints.
IEEE Trans. Very Large Scale Integr. Syst., 2013

CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast-Yet-Accurate Statistical Soft-Error-Rate Analysis Considering Full-Spectrum Charge Collection.
IEEE Des. Test, 2013

Aging-aware statistical soft-error-rate analysis for nano-scaled CMOS designs.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Fall Detection by a SVM-Based Cloud System with Motion Sensors.
Proceedings of the Advanced Technologies, Embedded and Multimedia for Human-centric Computing, 2013

Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step.
Proceedings of the Design, Automation and Test in Europe, 2013

D<sup>2</sup>ENDIST-FM: Flow migration in routing of OpenFlow-based cloud networks.
Proceedings of the IEEE 2nd International Conference on Cloud Networking, 2013

Flow-and-VM Migration for Optimizing Throughput and Energy in SDN-Based Cloud Datacenter.
Proceedings of the IEEE 5th International Conference on Cloud Computing Technology and Science, 2013

Synthesizing multiple scan chains by cost-driven spectral ordering.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Statistical Soft Error Rate (SSER) Analysis for Scaled CMOS Designs.
ACM Trans. Design Autom. Electr. Syst., 2012

Diagnostic test-pattern generation targeting open-segment defects and its diagnosis flow.
IET Comput. Digit. Tech., 2012

Spatial-correlation-aware soft error rate analysis using quasi-importance sampling.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

D<sup>2</sup>ENDIST: Dynamic and disjoint ENDIST-based layer-2 routing algorithm for cloud datacenters.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming.
J. Electron. Test., 2011

2010
Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Monte-Carlo-based statistical soft error rate (SSER) analysis for the deep sub-micron era.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Portable simulation/emulation stimulus on an industrial-strength SoC.
Proceedings of the 2009 IEEE International Test Conference, 2009

Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning.
Proceedings of the 2009 IEEE International Test Conference, 2009

On soft error rate analysis of scaled CMOS designs - A statistical perspective.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Mining Unreachable Cross-Timeframe State-Pairs for Bounded Sequential Equivalence Checking.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008

2007
An incremental learning framework for estimating signal controllability in unit-level verification.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Simulation-Based Functional Test Generation for Embedded Processors.
IEEE Trans. Computers, 2006

Simulation-based functional test justification using a decision-digram-based Boolean data miner.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Extracting a Simplified View of Design Functionality Based on Vector Simulation.
Proceedings of the Hardware and Software, 2006

Extracting a simplified view of design functionality via vector simulation.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
On A Software-Based Self-Test Methodology and Its Application.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Simulation Data Mining for Functional Test Pattern Justification.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

On Generating Tests to Cover Diverse Worst-Case Timing Corners.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005


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