Luc Jaulmes

According to our database, Luc Jaulmes authored at least 10 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2025

Low-Level and NUMA-Aware Optimization for High-Performance Quantum Simulation.

Ali Rezaei, Luc Jaulmes, Maria Bahna, Oliver Thomson Brown, Antonio Barbalace

CoRR, June, 2025

Tensorize: Fast Synthesis of Tensor Programs from Legacy Code using Symbolic Tracing, Sketching and Solving.

Alexander Brauckmann, Luc Jaulmes, José Wesley de Souza Magalhães, Elizabeth Polgreen, Michael F. P. O'Boyle

Proceedings of the 23rd ACM/IEEE International Symposium on Code Generation and Optimization, 2025

2020

Runtime-guided ECC protection using online estimation of memory vulnerability.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Mattan Erez, Marc Casas

Proceedings of the International Conference for High Performance Computing, 2020

2019

Exploiting task-based programming models for resilience.

Luc Jaulmes

PhD thesis, 2019

A Vulnerability Factor for ECC-protected Memory.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers.

Luc Jaulmes, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas

IEEE Trans. Parallel Distributed Syst., 2018

Memory Vulnerability: A Case for Delaying Error Reporting.

Luc Jaulmes, Miquel Moretó, Mateo Valero, Marc Casas

CoRR, 2018

2015

Exploiting asynchrony from exact forward recovery for DUE in iterative solvers.

Luc Jaulmes, Marc Casas, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the International Conference for High Performance Computing, 2015

Runtime-Aware Architectures.

Marc Casas, Miquel Moretó, Lluc Alvarez, Emilio Castillo, Dimitrios Chasapis, Timothy Hayes, Luc Jaulmes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Jesús Labarta, Mateo Valero

Proceedings of the Euro-Par 2015: Parallel Processing, 2015

2013

Fast modulo 2ⁿ-1 and 2ⁿ;1 adder using carry-chain on FPGA.

Laurent-Stéphane Didier, Luc Jaulmes

Proceedings of the 2013 Asilomar Conference on Signals, 2013