Michael F. P. O'Boyle

According to our database1, Michael F. P. O'Boyle authored at least 121 papers between 1992 and 2018.

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Bibliography

2018
SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM.
CoRR, 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.
CoRR, 2018

MaxPair: Enhance OpenCL Concurrent Kernel Execution by Weighted Maximum Matching.
Proceedings of the 11th Workshop on General Purpose Processing using GPUs, 2018

A Cross-platform Evaluation of Graphics Shader Compiler Optimization.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

Algorithmic Performance-Accuracy Trade-off in 3D Vision Applications.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

SLAMBench2: Multi-Objective Head-to-Head Benchmarking for Visual SLAM.
Proceedings of the 2018 IEEE International Conference on Robotics and Automation, 2018

CAnDL: a domain specific language for compiler analysis.
Proceedings of the 27th International Conference on Compiler Construction, 2018

Automatic Matching of Legacy Code to Heterogeneous APIs: An Idiomatic Approach.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Merge or Separate?: Multi-job Scheduling for OpenCL Kernels on CPU/GPU Platforms.
Proceedings of the General Purpose GPUs, 2017

Discovery and exploitation of general reductions: a constraint based approach.
Proceedings of the 2017 International Symposium on Code Generation and Optimization, 2017

2016
Selecting Heterogeneous Cores for Diversity.
TACO, 2016

Four Metrics to Evaluate Heterogeneous Multicores.
TACO, 2016

Diplomat: Mapping of Multi-kernel Applications Using a Static Dataflow Abstraction.
Proceedings of the 24th IEEE International Symposium on Modeling, 2016

Portable and transparent software managed scheduling on accelerators for fair resource sharing.
Proceedings of the 2016 International Symposium on Code Generation and Optimization, 2016

Integrating Algorithmic Parameters into Benchmarking and Design Space Exploration in 3D Scene Understanding.
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015
Celebrating diversity: a mixture of experts approach for runtime mapping in dynamic environments.
Proceedings of the 36th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2015

PALMOS: A Transparent, Multi-tasking Acceleration Layer for Parallel Heterogeneous Systems.
Proceedings of the 29th ACM on International Conference on Supercomputing, 2015

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.
Proceedings of the IEEE International Conference on Robotics and Automation, 2015

2014
Integrating profile-driven parallelism detection and machine-learning-based mapping.
TACO, 2014

Automatic and Portable Mapping of Data Parallel Programs to OpenCL for GPU-Based Heterogeneous Systems.
TACO, 2014

Automatic feature generation for machine learning-based optimising compilation.
TACO, 2014

Introducing SLAMBench, a performance and accuracy benchmarking methodology for SLAM.
CoRR, 2014

Partitioning data-parallel programs for heterogeneous MPSoCs: time and energy design space exploration.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

Change Detection Based Parallelism Mapping: Exploiting Offline Models and Online Adaptation.
Proceedings of the Languages and Compilers for Parallel Computing, 2014

Smart multi-task scheduling for OpenCL programs on CPU/GPU heterogeneous platforms.
Proceedings of the 21st International Conference on High Performance Computing, 2014

Portable and Transparent Host-Device Communication Optimization for GPGPU Environments.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014

Exploitation of GPUs for the Parallelisation of Probably Parallel Legacy Code.
Proceedings of the Compiler Construction - 23rd International Conference, 2014

A compiler framework for automatically mapping data parallel programs to heterogeneous MPSoCs.
Proceedings of the 2014 International Conference on Compilers, 2014

Exploiting GPU Hardware Saturation for Fast Compiler Optimization.
Proceedings of the Seventh Workshop on General Purpose Processing Using GPUs, 2014

Measuring flexibility in single-ISA heterogeneous processors.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

Automatic optimization of thread-coarsening for graphics processors.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Using machine learning to partition streaming programs.
TACO, 2013

A large-scale cross-architecture evaluation of thread-coarsening.
Proceedings of the International Conference for High Performance Computing, 2013

OpenCL Task Partitioning in the Presence of GPU Contention.
Proceedings of the Languages and Compilers for Parallel Computing, 2013

Portable mapping of data parallel programs to OpenCL for heterogeneous systems.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

Smart, adaptive mapping of parallelism in the presence of external workload.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

General chairs' welcome message.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Exploring and Predicting the Effects of Microarchitectural Parameters and Compiler Optimizations on Performance and Energy.
ACM Trans. Embedded Comput. Syst., 2012

2011
Compiler Directed Issue Queue Energy Reduction.
Trans. HiPEAC, 2011

An Empirical Architecture-Centric Approach to Microarchitectural Design Space Exploration.
IEEE Trans. Computers, 2011

Milepost GCC: Machine Learning Enabled Self-tuning Compiler.
International Journal of Parallel Programming, 2011

A workload-aware mapping approach for data-parallel programs.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

A Static Task Partitioning Approach for Heterogeneous Systems Using OpenCL.
Proceedings of the Compiler Construction - 20th International Conference, 2011

2010
A Predictive Model for Dynamic Microarchitectural Adaptivity Control.
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010

Partitioning streaming parallelism for multi-cores: a machine learning based approach.
Proceedings of the 19th International Conference on Parallel Architecture and Compilation Techniques, 2010

2009
Energy-efficient register caching with compiler assistance.
TACO, 2009

Exploring the limits of early register release: Exploiting compiler analysis.
TACO, 2009

Obituary: Peter Knijnenburg (1961-2007).
Concurrency and Computation: Practice and Experience, 2009

Mapping parallelism to multi-cores: a machine learning based approach.
Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009

Towards a holistic approach to auto-parallelization: integrating profile-driven parallelism detection and machine-learning based mapping.
Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009

Portable compiler optimisation across embedded programs and microarchitectures using machine learning.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Raced profiles: efficient selection of competing compiler optimizations.
Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, 2009

Reducing Training Time in a One-Shot Machine Learning-Based Compiler.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

Rapid early-stage microarchitecture design using predictive models.
Proceedings of the 27th International Conference on Computer Design, 2009

Automatic Feature Generation for Machine Learning Based Optimizing Compilation.
Proceedings of the CGO 2009, 2009

2008
Instruction Cache Energy Saving Through Compiler Way-Placement.
Proceedings of the Design, Automation and Test in Europe, 2008

Exploring and predicting the architecture/optimising compiler co-design space.
Proceedings of the 2008 International Conference on Compilers, 2008

2007
Introduction to Part 2.
Trans. HiPEAC, 2007

Quick and Practical Run-Time Evaluation of Multiple Program Optimizations.
Trans. HiPEAC, 2007

High-Performance Embedded Architecture and Compilation Roadmap.
Trans. HiPEAC, 2007

Microarchitectural Design Space Exploration Using an Architecture-Centric Approach.
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007

MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization.
Proceedings of the High Performance Embedded Architectures and Compilers, 2007

Topic 4 High-Performance Architectures and Compilers.
Proceedings of the Euro-Par 2007, 2007

Rapidly Selecting Good Compiler Optimizations using Performance Counters.
Proceedings of the Fifth International Symposium on Code Generation and Optimization (CGO 2007), 2007

Fast compiler optimisation evaluation using code-feature based performance prediction.
Proceedings of the 4th Conference on Computing Frontiers, 2007

2006
Method-specific dynamic compilation using logistic regression.
Proceedings of the 21th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2006

Predictive search distributions.
Proceedings of the Machine Learning, 2006

Using Machine Learning to Focus Iterative Optimization.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

Hybrid Optimizations: Which Optimization Algorithm to Use?.
Proceedings of the Compiler Construction, 15th International Conference, 2006

Iterative Collective Loop Fusion.
Proceedings of the Compiler Construction, 15th International Conference, 2006

Automatic performance model construction for the fast software exploration of new hardware designs.
Proceedings of the 2006 International Conference on Compilers, 2006

2005
A Complete Compiler Approach to Auto-Parallelizing C Programs for Multi-DSP Systems.
IEEE Trans. Parallel Distrib. Syst., 2005

IATAC: a smart predictor to turn-off L2 cache lines.
TACO, 2005

Automatic Tuning of Inlining Heuristics.
Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Probabilistic source-level optimisation of embedded programs.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

Software Directed Issue Queue Power Reduction.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

A Practical Method for Quickly Evaluating Program Optimizations.
Proceedings of the High Performance Embedded Architectures and Compilers, 2005

Topic 4 - Compilers for High Performance.
Proceedings of the Euro-Par 2005, Parallel Processing, 11th International Euro-Par Conference, Lisbon, Portugal, August 30, 2005

Compiler Directed Early Register Release.
Proceedings of the 14th International Conference on Parallel Architecture and Compilation Techniques (PACT 2005), 2005

2004
The effect of cache models on iterative compilation for combined tiling and unrolling.
Concurrency and Computation: Practice and Experience, 2004

A fast and accurate method for determining a lower bound on execution time.
Concurrency and Computation: Practice and Experience, 2004

Adaptive Java optimisation using instance-based learning.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

Topic 4: Compilers for High Performance.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Cross Component Optimisation in a High Level Category-Based Language.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.
The Journal of Supercomputing, 2003

Array recovery and high-level transformations for DSP applications.
ACM Trans. Embedded Comput. Syst., 2003

Towards general and exact distributed invalidation.
J. Parallel Distrib. Comput., 2003

Topic Introduction.
Proceedings of the Euro-Par 2003. Parallel Processing, 2003

Compiler parallelization of C programs for multi-core DSPs with multiple address spaces.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Combining Program Recovery, Auto-Parallelisation and Locality Analysis for C Programs on Multi-Processor Embedded Systems.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Compile Time Barrier Synchronization Minimization.
IEEE Trans. Parallel Distrib. Syst., 2002

Integrating Loop and Data Transformations for Global Optimization.
J. Parallel Distrib. Comput., 2002

Iterative Compilation.
Proceedings of the Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, 2002

Evaluating Iterative Compilation.
Proceedings of the Languages and Compilers for Parallel Computing, 15th Workshop, 2002

2001
Topic 04: Compilers for High Performance.
Proceedings of the Euro-Par 2001: Parallel Processing, 2001

Compiler Transformation of Pointers to Explicit Array Accesses in DSP Applications.
Proceedings of the Compiler Construction, 10th International Conference, 2001

An empirical evaluation of high level transformations for embedded processors.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
Exact Distributed Invalidation.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000

Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation.
Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), 2000

1999
Nonsingular Data Transformations: Definition, Validity, and Applications.
International Journal of Parallel Programming, 1999

A Feasibility Study in Iterative Compilation.
Proceedings of the High Performance Computing, Second International Symposium, 1999

OCEANS - Optimising Compilers for Embedded Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

Efficient Parallelization Using Combined Loop and Data Transformations.
Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, 1999

1998
First Fast Sink: A compiler algorithm for barrier placement optimisation.
Future Generation Comp. Syst., 1998

MARS: A Distributed Memory Approach to Shared Memory Compilation.
Proceedings of the Languages, 1998


Integrating Loop and Data Transformations for Global Optimization.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
A Graph Based Approach to Barrier Synchronisation Minimisation.
Proceedings of the 11th international conference on Supercomputing, 1997

Non-Singular Data Transformations: Definition, Validity and Applications.
Proceedings of the 11th international conference on Supercomputing, 1997

Barrier Synchronisation Optimisation.
Proceedings of the High-Performance Computing and Networking, 1997


1996
Expert Programmer versus Parallelizing Compiler: A Comparative Study of Two Approaches for Distributed Shared Memory.
Scientific Programming, 1996

Practical Loop Generation.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

Compiler Reduction of Invalidation Traffic in Virtual Shared Memory Systems.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

A compiler algorithm to reduce invalidation latency in virtual shared memory systems.
Proceedings of the Fifth International Conference on Parallel Architectures and Compilation Techniques, 1996

1995
Synchronization Minimization in a SPMD Execution Model.
J. Parallel Distrib. Comput., 1995

A hierarchical locality algorithm for NUMA compilation.
Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), 1995

Compiler Reduction of Synchronisation in Shared Virtual Memory Systems.
Proceedings of the 9th international conference on Supercomputing, 1995

1994
A Data Partitioning Algorithm for Distributed Memory Compilation.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

1992
A New Program Transformation to Minimise Communication in Distributed Memory Architecture.
Proceedings of the PARLE '92: Parallel Architectures and Languages Europe, 1992

A transformational approach to compiling Sisal for distributed memory architectures.
Proceedings of the 6th international conference on Supercomputing, 1992


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