Oscar Palomar

Orcid: 0000-0001-6729-4187

Affiliations:

Barcelona Supercomputing Center, Barcelona, Spain

According to our database¹, Oscar Palomar authored at least 60 papers between 2009 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2023

Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., June, 2023

Functional Verification of a RISC-V Vector Accelerator.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

FAUST: Design and implementation of a pipelined RISC-V vector floating-point unit.

[BibT_eX]

[DOI]

Microprocess. Microsystems, March, 2023

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology.

[BibT_eX]

[DOI]

Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023

eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

2020

A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.

[BibT_eX]

[DOI]

Cristóbal Ramírez

César-Alejandro Hernández-Calderón

Oscar Palomar

Osman S. Unsal

Marco Antonio Ramírez

Adrián Cristal

ACM Trans. Archit. Code Optim., 2020

Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020).

[BibT_eX]

[DOI]

Miquel Pericàs

Oscar Palomar

Vassilis Papaefstathiou

Mahmoud Eljammaly

CoRR, 2020

2019

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs.

[BibT_eX]

[DOI]

Konstantinos Iordanou

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

Memory Controller for Vector Processor.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2018

Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Navigating the Landscape for Real-Time Localization and Mapping for Robotics and Virtual and Augmented Reality.

[BibT_eX]

[DOI]

Proc. IEEE, 2018

Navigating the Landscape for Real-time Localisation and Mapping for Robotics and Virtual and Augmented Reality.

[BibT_eX]

[DOI]

CoRR, 2018

2017

An Integrated Vector-Scalar Design on an In-Order ARM Core.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2017

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2016

Architectural support for efficient message passing on shared memory multi-cores.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2016

Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory.

[BibT_eX]

[DOI]

Comput. Sci. Eng., 2016

Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.

[BibT_eX]

[DOI]

Gulay Yalcin

Santhosh Kumar Rethinagiri

Proceedings of the 24th Euromicro International Conference on Parallel, 2016

A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Future Vector Microprocessor Extensions for Data Aggregations.

[BibT_eX]

[DOI]

Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Energy minimization at all layers of the data center: The ParaDIME project.

[BibT_eX]

[DOI]

Oscar Palomar

Santhosh Kumar Rethinagiri

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Towards low-power embedded vector processor.

[BibT_eX]

[DOI]

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

POSTER: An Integrated Vector-Scalar Design on an In-order ARM Core.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

2015

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Microprocess. Microsystems, 2015

FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Imposing coarse-grained reconfiguration to general purpose processors.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

DiMP: Architectural Support for Direct Message Passing on Shared Memory Multi-cores.

[BibT_eX]

[DOI]

Proceedings of the 44th International Conference on Parallel Processing, 2015

VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Trigeneous Platforms for Energy Efficient Computing of HPC Applications.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015

Heterogeneous Platform to Accelerate Compute Intensive Applications.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Runtime-Aware Architectures.

[BibT_eX]

[DOI]

Proceedings of the Euro-Par 2015: Parallel Processing, 2015

An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015

ViPS: Visual processing system for medical imaging.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Biomedical Engineering and Informatics, 2015

2014

DESSERT: DESign Space ExploRation Tool based on power and energy at System-Level.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Dynamic-vector execution on a general purpose EDGE chip multiprocessor.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

PAMS: Pattern Aware Memory System for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

System-level power estimation tool for embedded processor based platforms.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Adrián Cristal Kestelman

Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Morteza Biglari-Abhari

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

PETS: Power and energy estimation tool at system-level.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Evaluation of vectorization potential of Graph500 on Intel's Xeon Phi.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2014

Advanced Pattern based Memory Controller for FPGA based HPC applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2014

AMMC: Advanced Multi-Core Memory Controller.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

MAPC: Memory access pattern based controller.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Power estimation tool for system on programmable chip based platforms (abstract only).

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Oscar Palomar

Adrián Cristal

Osman S. Unsal

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

APMC: advanced pattern based memory controller (abstract only).

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy.

[BibT_eX]

[DOI]

Santhosh Kumar Rethinagiri

Oscar Palomar

Anita Sobe

Thomas Knauth

Wojciech M. Barczynski

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

EVX: Vector execution on low power EDGE cores.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

VALib and SimpleVector: tools for rapid initial research on vector architectures.

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, CF'14, 2014

PVMC: Programmable Vector Memory Controller.

[BibT_eX]

[DOI]

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

Stand-Alone Memory Controller for Graphics System.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

ReCompAc: Reconfigurable compute accelerator.

[BibT_eX]

[DOI]

Milovan Duric

Oscar Palomar

Aaron Smith

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

On the selection of adder unit in energy efficient vector processing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

2012

Vector Extensions for Decision Support DBMS Acceleration.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011

Reusing cached schedules in an out-of-order processor with in-order issue logic.

[BibT_eX]

[DOI]

Oscar Palomar

PhD thesis, 2011

2009

Reusing cached schedules in an out-of-order processor with in-order issue logic.

[BibT_eX]

[DOI]

Oscar Palomar

Toni Juan

Juan J. Navarro

Proceedings of the 27th International Conference on Computer Design, 2009

Oscar Palomar

Timeline

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Bibliography

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