Adrián Cristal
Orcid: 0000-0003-1277-9296
According to our database1,
Adrián Cristal
authored at least 205 papers
between 2003 and 2023.
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Bibliography
2023
Vitruvius+: An Area-Efficient RISC-V Decoupled Vector Coprocessor for High Performance Computing Applications.
ACM Trans. Archit. Code Optim., June, 2023
Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Micro, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
BiSon-e: a lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge.
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
2021
VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Towards Zero-Waste Recovery and Zero-Overhead Checkpointing in Ensemble Data Assimilation.
Proceedings of the 28th IEEE International Conference on High Performance Computing, 2021
Understanding Power Consumption and Reliability of High-Bandwidth Memory with Voltage Underscaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures.
ACM Trans. Archit. Code Optim., 2020
CoRR, 2020
Power and Accuracy of Multi-Layer Perceptrons (MLPs) under Reduced-voltage FPGA BRAMs Operation.
CoRR, 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration.
Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2020
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
CoRR, 2019
TauRieL: Targeting Traveling Salesman Problem with a deep reinforcement learning inspired architecture.
CoRR, 2019
Evaluating Built-In ECC of FPGA On-Chip Memories for the Mitigation of Undervolting Faults.
Proceedings of the 27th Euromicro International Conference on Parallel, 2019
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019
Ground-Truth Prediction to Accelerate Soft-Error Impact Analysis for Iterative Methods.
Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019
2018
Vector Processing-Aware Advanced Clock-Gating Techniques for Low-Power Fused Multiply-Add.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Exploring the capabilities of support vector machines in detecting silent data corruptions.
Sustain. Comput. Informatics Syst., 2018
Supercomput. Front. Innov., 2018
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
ACM Trans. Archit. Code Optim., 2017
Int. J. Parallel Program., 2017
IEEE Comput. Archit. Lett., 2017
A Machine Learning Approach for Performance Prediction and Scheduling on Heterogeneous CPUs.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017
RETHINK big: European roadmap for hardware anc networking optimizations for big data.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 2017 IEEE International Conference on Cluster Computing, 2017
Proceedings of the High Performance Computing - 4th Latin American Conference, 2017
2016
J. Parallel Distributed Comput., 2016
Implications of non-volatile memory as primary storage for database management systems.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
A Fully Parameterizable Low Power Design of Vector Fused Multiply-Add Using Active Clock-Gating Techniques.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016
Proceedings of the IEEE/ACM 16th International Symposium on Cluster, 2016
Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique.
Proceedings of the High Performance Computing - Third Latin American Conference, 2016
Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016
Proceedings of the FPGAs for Software Programmers, 2016
2015
ACM Trans. Parallel Comput., 2015
Parallel Comput., 2015
Reimagining Heterogeneous Computing: A Functional Instruction-Set Architecture Computing Model.
IEEE Micro, 2015
ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers.
Microprocess. Microsystems, 2015
IEEE Comput. Archit. Lett., 2015
Chapter One - An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques.
Adv. Comput., 2015
FAcET: Fast and accurate power/energy estimation tool for CPU-GPU platforms at architectural-level.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
Performance and Energy Efficient Hardware-Based Scheduler for Symmetric/Asymmetric CMPs.
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
NanoCheckpoints: A Task-Based Asynchronous Dataflow Framework for Efficient and Scalable Checkpoint/Restart.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015
NEMsCAM: A novel CAM cell based on nano-electro-mechanical switch and CMOS for energy efficient TLBs.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015
Joint Circuit-System Design Space Exploration of Multiplier Unit Structure for Energy-Efficient Vector Processors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
JSRAM: A Circuit-Level Technique for Trading-Off Robustness and Capacity in Cache Memories.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 44th International Conference on Parallel Processing, 2015
VPM: Virtual power meter tool for low-power many-core/heterogeneous data center prototypes.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
VSR sort: A novel vectorised sorting algorithm & architecture extensions for future microprocessors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 22nd IEEE International Conference on High Performance Computing, 2015
Proceedings of the 12th FPGAworld Conference 2015, 2015
Accelerating Complete Decision Support Queries Through High-Level Synthesis Technology (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015
Proceedings of the Euro-Par 2015: Parallel Processing, 2015
Proceedings of the Euro-Par 2015: Parallel Processing, 2015
Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015
An energy efficient hybrid FPGA-GPU based embedded platform to accelerate face recognition application.
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
Proceedings of the 12th ACM International Conference on Computing Frontiers, 2015
Proceedings of the 8th International Conference on Biomedical Engineering and Informatics, 2015
2014
ACM Trans. Archit. Code Optim., 2014
Microprocess. Microsystems, 2014
Int. J. Parallel Program., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
A Case Study of Hybrid Dataflow and Shared-Memory Programming Models: Dependency-Based Parallel Game Engine.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Proceedings of the Runtime Verification - 5th International Conference, 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 2014 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2014
Combining Error Detection and Transactional Memory for Energy-Efficient Computing below Safe Operation Margins.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
System-Level Power and Energy Estimation Methodology for Open Multimedia Applications Platforms.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Physical vs. Physically-Aware Estimation Flow: Case Study of Design Space Exploration of Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
Proceedings of the International Conference on High Performance Computing & Simulation, 2014
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
An empirical evaluation of High-Level Synthesis languages and tools for database acceleration.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Power estimation tool for system on programmable chip based platforms (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the Ninth Eurosys Conference 2014, 2014
System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms.
Proceedings of the 12th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
Proceedings of the Computing Frontiers Conference, CF'14, 2014
DaSH: a benchmark suite for hybrid dataflow and shared memory programming models: with comparative evaluation of three hybrid dataflow models.
Proceedings of the Computing Frontiers Conference, CF'14, 2014
Proceedings of the High Performance Computing - First HPCLATAM, 2014
Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014
2013
Profile-guided transaction coalescing - lowering transactional overheads by merging transactions.
ACM Trans. Archit. Code Optim., 2013
ACM Trans. Archit. Code Optim., 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 27th IEEE International Symposium on Parallel and Distributed Processing, 2013
Proceedings of the International Conference on Computational Science, 2013
Proceedings of the 20th Annual International Conference on High Performance Computing, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Fault tolerance for multi-threaded applications by leveraging hardware transactional memory.
Proceedings of the Computing Frontiers Conference, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Int. J. Parallel Program., 2012
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the Runtime Verification, Third International Conference, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Enhancing the performance of assisted execution runtime systems through hardware/software techniques.
Proceedings of the International Conference on Supercomputing, 2012
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Transactional prefetching: narrowing the window of contention in hardware transactional memory.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
RMS-TM: a comprehensive benchmark suite for transactional memory systems (abstracts only).
SIGMETRICS Perform. Evaluation Rev., 2011
Int. J. Parallel Program., 2011
Proceedings of the ICPE'11, 2011
Rapid Development of Error-Free Architectural Simulators Using Dynamic Runtime Testing.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011
Proceedings of the IEEE 29th International Conference on Computer Design, 2011
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011
SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010
2009
Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009
Turbocharging boosted transactions or: how i learnt to stop worrying and love longer transactions.
Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Taking the heat off transactions: Dynamic selection of pessimistic concurrency control.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Dynamically Filtering Thread-Local Variables in Lazy-Lazy Hardware Transactional Memory.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009
2008
Int. J. Parallel Program., 2008
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008
Proceedings of the 9th workshop on MEmory performance, 2008
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment.
Proceedings of the 5th Conference on Computing Frontiers, 2008
2007
unreadTVar: Extending Haskell Software Transactional Memory for Performance.
Proceedings of the Eighth Symposium on Trends in Functional Programming, 2007
Proceedings of the 2007 workshop on MEmory performance, 2007
Proceedings of the A Practical Programming Model for the Multi-Core Era, 2007
Proceedings of the Euro-Par 2007 Workshops: Parallel Processing, 2007
Proceedings of the Advances in Computer Systems Architecture, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006
2005
Proceedings of the 17th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2005), 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Proceedings of the 19th Annual International Conference on Supercomputing, 2005
Proceedings of the International Conference on Pervasive Services 2005, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
2004
A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors.
SIGARCH Comput. Archit. News, 2004
Int. J. High Perform. Comput. Netw., 2004
Proceedings of the 3rd Workshop on Memory Performance Issues, 2004
Proceedings of the Power-Aware Computer Systems, 4th International Workshop, 2004
Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
IEEE Comput. Archit. Lett., 2003
Proceedings of the High Performance Computing, 5th International Symposium, 2003
Proceedings of the High Performance Computing, 5th International Symposium, 2003