Lluc Alvarez

Orcid: 0000-0003-0506-8867

According to our database1, Lluc Alvarez authored at least 37 papers between 2009 and 2024.

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Bibliography

2024
A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
WFA-FPGA: An efficient accelerator of the wavefront algorithm for short and long read genomics alignment.
Future Gener. Comput. Syst., December, 2023

Adaptive Power Shifting for Power-Constrained Heterogeneous Systems.
IEEE Trans. Computers, March, 2023

Characterizing the impact of last-level cache replacement policies on big-data workloads.
CoRR, 2023

OpenPiton Optimizations Towards High Performance Manycores.
Proceedings of the 16th International Workshop on Network on Chip Architectures, 2023

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC.
Proceedings of the 52nd International Conference on Parallel Processing, 2023

Accelerators in Embedded Systems for Machine Learning: A RISCV View.
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023


2022
Accelerating Edit-Distance Sequence Alignment on GPU Using the Wavefront Algorithm.
IEEE Access, 2022

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models.
Proceedings of the SC22: International Conference for High Performance Computing, 2022

Page Size Aware Cache Prefetching.
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

A review of CNN accelerators for embedded systems based on RISC-V.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022

2021
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption.
IEEE Trans. Computers, 2021

Morrigan: A Composite Instruction TLB Prefetcher.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Exploiting Page Table Locality for Agile TLB Prefetching.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
Characterizing the impact of last-level cache replacement policies on big-data workloads.
Proceedings of the IEEE International Symposium on Workload Characterization, 2020

The DeepHealth Toolkit: A Unified Framework to Boost Biomedical Applications.
Proceedings of the 25th International Conference on Pattern Recognition, 2020

A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2018
Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach.
IEEE Trans. Parallel Distributed Syst., 2018

Runtime-assisted cache coherence deactivation in task parallel programs.
Proceedings of the International Conference for High Performance Computing, 2018

Peachy Parallel Assignments (EduHPC 2018).
Proceedings of the 2018 IEEE/ACM Workshop on Education for High-Performance Computing, 2018

Teaching HPC Systems and Parallel Programming with Small-Scale Clusters.
Proceedings of the 2018 IEEE/ACM Workshop on Education for High-Performance Computing, 2018

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks.
Proceedings of the 2018 IEEE International Symposium on Workload Characterization, 2018

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs.
Proceedings of the 32nd International Conference on Supercomputing, 2018

Architectural Support for Task Dependence Management with Flexible Software Scheduling.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2016
CATA: Criticality Aware Task Acceleration for Multicore Processors.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium, 2016

2015
Transparent management of scratchpad memories in shared memory programming models.
PhD thesis, 2015

Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories.
IEEE Trans. Computers, 2015

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015


Runtime-Guided Management of Scratchpad Memories in Multicore Architectures.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2012
DMA-circular: an enhanced high level programmable DMA controller for optimized management of on-chip local memories.
Proceedings of the Computing Frontiers Conference, CF'12, 2012

2011
Design space exploration for aggressive core replication schemes in CMPs.
Proceedings of the 20th ACM International Symposium on High Performance Distributed Computing, 2011

2009
Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories.
Proceedings of the Languages and Compilers for Parallel Computing, 2009

Cetra: A trace and analysis framework for the evaluation of Cell BE systems.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009


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