Luca Fanori

According to our database1, Luca Fanori authored at least 15 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2019
A Wideband Saw-Less Transmitter Operating in Closed-Loop With Embedded N-Path Filtering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

2014
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers.
IEEE J. Solid State Circuits, 2014

21.6 A 2.4-to-5.3GHz dual-core CMOS VCO with concentric 8-shaped coils.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A Class-D CMOS DCO with an on-chip LDO.
Proceedings of the ESSCIRC 2014, 2014

2013
Class-D CMOS Oscillators.
IEEE J. Solid State Circuits, 2013

Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs.
IEEE J. Solid State Circuits, 2013

A 2.5-to-3.3GHz CMOS Class-D VCO.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

A high-swing complementary class-C VCO.
Proceedings of the ESSCIRC 2013, 2013

2012
A Dither-Less All Digital PLL for Cellular Transmitters.
IEEE J. Solid State Circuits, 2012

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

Low-phase-noise 3.4-4.5 GHz dynamic-bias class-C CMOS VCOs with a FoM of 191 dBc/Hz.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Dynamic bias schemes for class-C VCOs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

2010
Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning.
IEEE J. Solid State Circuits, 2010

3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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