Antonio Liscidini

According to our database1, Antonio Liscidini authored at least 49 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

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Online presence:

On csauthors.net:

Bibliography

2020
Temperature Compensation of Crystal References in NB-IoT Modems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

2019
A Third-Order Integrated Passive Switched-Capacitor Filter Obtained With a Continuous-Time Design Approach.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Quantized Analog RF Front End.
IEEE J. Solid State Circuits, 2019

2018
A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers.
IEEE J. Solid State Circuits, 2018

Quantized Analog RX Front-End for SAW-Less Applications.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

Low-Power QPSK Transmitter Based on an Injection-Locked Power Amplifier.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

A low-power sub-GHz RF receiver front-end with enhanced blocker tolerance.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Filtering ADCs for wireless receivers: A survey.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

F4: Wireless low-power transceivers for local and wide-area networks.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A LTE RX front-end with digitally programmable multi-band blocker cancellation in 28nm CMOS.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
A Simplified Model for Passive-Switched-Capacitor Filters With Complex Poles.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Introduction to the December Special Issue on the 2016 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2016

Class-C PA-VCO Cell for FSK and GFSK Transmitters.
IEEE J. Solid State Circuits, 2016

20.9 A 1.92mW filtering transimpedance amplifier for RF current passive mixers.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2015
Current-Recycling Complex Filter for Bluetooth-Low-Energy Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Sub-mW Current Re-Use Receiver Front-End for Wireless Sensor Network Applications.
IEEE J. Solid State Circuits, 2015

13.6 A 600μW Bluetooth low-energy front-end receiver in 0.13μm CMOS technology.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Bluetooth low energy receiver system design.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A current re-use PA-VCO cell for low-power BLE transmitters.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers.
IEEE J. Solid State Circuits, 2014

An Intuitive Analysis of Phase Noise Fundamental Limits Suitable for Benchmarking LC Oscillators.
IEEE J. Solid State Circuits, 2014

A Current-Mode, Low Out-of-Band Noise LTE Transmitter With a Class-A/B Power Mixer.
IEEE J. Solid State Circuits, 2014

2013
An Intuitive Current-Driven Passive Mixer Model Based on Switched-Capacitor Theory.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

Introduction to the Special Issue on the 38th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2013

SAW-Less Analog Front-End Receivers for TDD and FDD.
IEEE J. Solid State Circuits, 2013

An LTE transmitter using a class-A/B power mixer.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

F5: Frequency generation and clock distribution.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
A 2G/3G Cellular Analog Baseband Based on a Filtering ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

A Dither-Less All Digital PLL for Cellular Transmitters.
IEEE J. Solid State Circuits, 2012

A 3.6 mW, 90 nm CMOS Gated-Vernier Time-to-Digital Converter With an Equivalent Resolution of 3.2 ps.
IEEE J. Solid State Circuits, 2012

Clock/Frequency Generation Circuits and Systems.
J. Electr. Comput. Eng., 2012

A 90nm CMOS gated-ring-oscillator-based 2-dimension Vernier time-to-digital converter.
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012

A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Corrections to "Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping" [Sep 10 1770-1780].
IEEE J. Solid State Circuits, 2011

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A 90nm CMOS gated-ring-oscillator-based Vernier time-to-digital converter for DPLLs.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

2010
Two-Dimensions Vernier Time-to-Digital Converter.
IEEE J. Solid State Circuits, 2010

Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications.
IEEE J. Solid State Circuits, 2010

Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping.
IEEE J. Solid State Circuits, 2010

Capacitive Degeneration in LC-Tank Oscillator for DCO Fine-Frequency Tuning.
IEEE J. Solid State Circuits, 2010

3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 1.25mW 75dB-SFDR CT filter with in-band noise reduction.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Time to digital converter based on a 2-dimensions Vernier architecture.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Analysis and Design of Configurable LNAs in Feedback Common-Gate Topologies.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 2.4 GHz 3.6mW 0.35mm<sup>2</sup> Quadrature Front-End RX for ZigBee and WPAN Applications.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 0.23mm2 free coil ZigBee receiver based on a bond-wire self-oscillating mixer.
Proceedings of the ESSCIRC 2008, 2008

2006
A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Common Gate Transformer Feedback LNA in a High IIP3 Current Mode RF CMOS Front-End.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006


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