Luis Andrés Cardona

According to our database, Luis Andrés Cardona authored at least 6 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.

Anees Ullah, Ernesto Sánchez, Luca Sterpone, Luis Andrés Cardona, Carles Ferrer

Microelectron. Reliab., 2017

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.

Luis Andrés Cardona, Anees Ullah, Luca Sterpone, Carles Ferrer

J. Syst. Archit., 2017

2016

Dynamic partial reconfiguration in fpgas for the design and evaluation of critical systems.

Luis Andrés Cardona

PhD thesis, 2016

2015

AC_ICAP: A Flexible High Speed ICAP Controller.

Luis Andrés Cardona, Carles Ferrer

Int. J. Reconfigurable Comput., 2015

2014

Partial crypto-reconfiguration of nodes based on FPGA for WSN.

Luis Andrés Cardona, B. Lorente, Carles Ferrer

Proceedings of the International Carnahan Conference on Security Technology, 2014

2011

Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application.

Luis Andrés Cardona, Jharna Agrawal, Yi Guo, Joan Oliver, Carles Ferrer

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011