Ernesto Sánchez
Orcid: 0000-0002-7042-295XAffiliations:
- Politecnico di Torino, Italy
According to our database1,
Ernesto Sánchez
authored at least 178 papers
between 2003 and 2023.
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Bibliography
2023
Computer, February, 2023
Proceedings of the 41st IEEE VLSI Test Symposium, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
A Fast Reliability Analysis of Image Segmentation Neural Networks Exploiting Statistical Fault Injections.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Image Test Libraries for the on-line self-test of functional units in GPUs running CNNs.
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Uncovering hidden vulnerabilities in CNNs through evolutionary-based Image Test Libraries.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks.
IEEE Trans. Emerg. Top. Comput., 2022
CAN-MM: Multiplexed Message Authentication Code for Controller Area Network message authentication in road vehicles.
CoRR, 2022
Machine learning for hardware security: Classifier-based identification of Trojans in pipelined microprocessors.
Appl. Soft Comput., 2022
Proceedings of the IEEE International Test Conference in Asia, 2022
LIN-MM: Multiplexed Message Authentication Code for Local Interconnect Network message authentication in road vehicles.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022
2021
Investigating data representation for efficient and reliable Convolutional Neural Networks.
Microprocess. Microsystems, October, 2021
Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
A JTAG-based Fault Emulation Platform for Dependability Analyses of Processor-based ASICs.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
A Suitability Analysis of Software Based Testing Strategies for the On-line Testing of Artificial Neural Networks Applications in Embedded Devices.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Mitigation of Automotive Control Modules Hardware Replacement-based Attacks Through Hardware Signature.
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Simulation and Formal: The Best of Both Domains for Instruction Set Verification of RISC-V Based Processors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Design, Verification, Test and In-Field Implications of Approximate Computing Systems.
Proceedings of the IEEE European Test Symposium, 2020
Evaluating Convolutional Neural Networks Reliability depending on their Data Representation.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-Chips.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Fault Grading Techniques of Software Test Libraries for Safety-Critical Applications.
IEEE Access, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
On the Detection of Always-On Hardware Trojans Supported by a Pre-Silicon Verification Methodology.
Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
A Decentralized Scheduler for On-line Self-test Routines in Multi-core Automotive System-on-Chips.
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the IEEE International Test Conference, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Hybrid on-line self-test architecture for computational units on embedded processor cores.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
J. Low Power Electron., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
On the Mitigation of Hardware Trojan Attacks in Embedded Processors by Exploiting a Hardware-Based Obfuscator.
Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018
Development flow of on-line Software Test Libraries for asynchronous processor cores.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Increasing reliability of safety critical applications through functional based solutions.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers.
Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
2017
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab., 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
On the development of a high-level fault simulator for the analysis of performance faults on speculative modules.
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
IEEE Trans. Computers, 2016
Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation.
Microprocess. Microsystems, 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016
Proceedings of the Applications of Evolutionary Computation - 19th European Conference, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Permanent fault detection and diagnosis in the lightweight dual modular redundancy architecture.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the Genetic and Evolutionary Computation Conference, 2015
Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015
Software-based self-test techniques of computational modules in dual issue embedded processors.
Proceedings of the 20th IEEE European Test Symposium, 2015
2014
MIHST: A Hardware Technique for Embedded Microprocessor Functional On-Line Self-Test.
IEEE Trans. Computers, 2014
Increasing the Fault Coverage of Processor Devices during the Operational Phase Functional Test.
J. Electron. Test., 2014
J. Electron. Test., 2014
Proceedings of the Symposium on Applied Computing, 2014
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation.
Proceedings of the Applications of Evolutionary Computation - 17th European Conference, 2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
On the in-field test of Branch Prediction Units using the correlated predictor mechanism.
Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014
2013
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption.
J. Low Power Electron., 2013
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
A software-based self-test strategy for on-line testing of the scan chain circuitries in embedded microprocessors.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
A functional test algorithm for the register forwarding and pipeline interlocking unit in pipelined microprocessors.
Proceedings of the 8th International Design and Test Symposium, 2013
On the on-line functional test of the Reorder Buffer memory in superscalar processors.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2012
Intelligent Systems Reference Library 34, Springer, ISBN: 978-3-642-27466-4, 2012
Proceedings of the 13th International Workshop on Microprocessor Test and Verification, 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the 17th IEEE European Test Symposium, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 21st IEEE Asian Test Symposium, 2012
2011
Increasing pattern recognition accuracy for chemical sensing by evolutionary based drift compensation.
Pattern Recognit. Lett., 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
On the Functional Test of Branch Prediction Units Based on the Branch History Table Architecture.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Automatic Generation of Software-based Functional Failing Test for Speed Debug and On-silicon Timing Verification.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011
Functional test generation for the pLRU replacement mechanism of embedded cache memories.
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Proceedings of the 13th Annual Genetic and Evolutionary Computation Conference, 2011
Proceedings of the Applications of Evolutionary Computation, 2011
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.
Proceedings of the 16th European Test Symposium, 2011
Fault grading of software-based self-test procedures for dependable automotive applications.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the IEEE Congress on Evolutionary Computation, 2011
2010
A Framework for Automated Detection of Power-related Software Errors in Industrial Verification Processes.
J. Electron. Test., 2010
Generating power-hungry test programs for power-aware validation of pipelined processors.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
An Enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
A Fault Grading Methodology for Software-Based Self-Test Programs in Systems-on-Chip.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the Genetic and Evolutionary Computation Conference, 2010
Proceedings of the Applications of Evolutionary Computation, 2010
Proceedings of the Applications of Evolutionary Computation, 2010
Proceedings of the 15th European Test Symposium, 2010
A hardware accelerated framework for the generation of design validation programs for SMT processors.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the Genetic and Evolutionary Computation Conference, 2009
Proceedings of the 14th IEEE European Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008
A Deterministic Methodology for Identifying Functionally Untestable Path-Delay Faults in Microprocessor Cores.
Proceedings of the Ninth International Workshop on Microprocessor Test and Verification, 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction.
Proceedings of the Applications of Evolutionary Computing, 2008
Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.
Proceedings of the Applications of Evolutionary Computing, 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2007
Evolutionary Techniques Applied to Hardware Optimization Problems: Test and Verification of Advanced Processors.
Proceedings of the Advances in Evolutionary Computing for System Design, 2007
A software-based methodology for the generation of peripheral test sets based on high-level descriptions.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
On Automatic Test Block Generation for Peripheral Testing in SoCs via Dynamic FSMs Extraction.
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Coupling EA and high-level metrics for the automatic generation of test blocks for peripheral cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2007
On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores.
Proceedings of the 12th European Test Symposium, 2007
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the IEEE Congress on Evolutionary Computation, 2007
Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007
2006
Int. J. Parallel Program., 2006
An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 2006 IEEE Symposium on Computational Intelligence and Games (CIG06), 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
Proceedings of the IEEE International Conference on Evolutionary Computation, 2006
2005
IEEE Trans. Evol. Comput., 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
New evolutionary techniques for test-program generation for complex microprocessor cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005
Proceedings of the Applications of Evolutionary Computing, 2005
On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
2004
J. Electron. Test., 2004
Proceedings of the Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), 2004
Proceedings of the Applications of Evolutionary Computing, 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
Proceedings of the IEEE Congress on Evolutionary Computation, 2004
2003
Proceedings of the IEEE Congress on Evolutionary Computation, 2003