Luca Sterpone
Orcid: 0000-0002-3080-2560
According to our database1,
Luca Sterpone
authored at least 172 papers
between 2004 and 2024.
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Bibliography
2024
CNN-Oriented Placement Algorithm for High-Performance Accelerators on Rad-Hard FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
2023
Fighting for a future free from violence: A framework for real-time detection of "Signal for Help".
Intell. Syst. Appl., 2023
Proceedings of the 19th International Conference on Synthesis, 2023
PyXEL: Exploring Bitstream Analysis to Assess and Enhance the Robustness of Designs on FPGAs.
Proceedings of the 19th International Conference on Synthesis, 2023
Proceedings of the IEEE International Symposium on Technology and Society, 2023
Design Techniques for Multi-Core Neural Network Accelerators on Radiation-Hardened FPGAs.
Proceedings of the 22nd International Symposium on Parallel and Distributed Computing, 2023
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
A Framework for Uniformly Analyze and Mitigate Radiation-effects on FPGAs for Aerospace.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
Assessing the Robustness of Real-Time Operating System on Soft Processor against Multiple Bit Upset.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
2022
Evaluating low-level software-based hardening techniques for configurable GPU architectures.
J. Supercomput., 2022
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Syst. J., 2022
A Placement-Oriented Mitigation Technique for Single Event Effect in Monolithic 3D IC.
Proceedings of the 18th International Conference on Synthesis, 2022
Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Proceedings of the IEEE European Test Symposium, 2022
Analysis of Proton-induced Single Event Effect in the On-Chip Memory of Embedded Process.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
On the Reliability of Real-Time Operating System on Embedded Soft Processor for Space Applications.
Proceedings of the Architecture of Computing Systems - 35th International Conference, 2022
2021
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication.
IEEE Trans. Very Large Scale Integr. Syst., 2021
J. Supercomput., 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source Embedded Static RAMs.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Access, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Evaluating Software-based Hardening Techniques for General-Purpose Registers on a GPGPU.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Machine Learning Clustering Techniques for Selective Mitigation of Critical Design Features.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs.
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020
RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the Architecture of Computing Systems - ARCS 2020, 2020
Soft-Error Analysis of Self-reconfiguration Controllers for Safety Critical Dynamically Reconfigurable FPGAs.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020
2019
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs.
Integr., 2019
Analyzing Radiation-Induced Transient Errors on SRAM-Based FPGAs by Propagation of Broadening Effect.
IEEE Access, 2019
A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs.
Proceedings of the 16th International Conference on Synthesis, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019
On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019
On the Reliability of Convolutional Neural Network Implementation on SRAM-based FPGA.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019
ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
OLT(RE)<sup>2</sup>: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.
IEEE Trans. Emerg. Top. Comput., 2018
Microelectron. Reliab., 2018
SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs.
Proceedings of the 15th International Conference on Synthesis, 2018
PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018
IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018
2017
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers, 2017
Microelectron. Reliab., 2017
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab., 2017
Microelectron. Reliab., 2017
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
J. Syst. Archit., 2017
Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment.
J. Syst. Archit., 2017
Proceedings of the IEEE International Test Conference, 2017
Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017
Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017
2016
IEEE Trans. Computers, 2016
Microelectron. Reliab., 2016
UA<sup>2</sup>TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.
Integr., 2016
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016
Proceedings of the 17th Latin-American Test Symposium, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies.
Microelectron. Reliab., 2015
On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015
SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectron. Reliab., 2014
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.
J. Electron. Test., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 19th IEEE European Test Symposium, 2014
Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
Proceedings of the 19th IEEE European Test Symposium, 2014
Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.
IEEE Trans. Computers, 2013
SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.
Microelectron. Reliab., 2013
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
On the optimized generation of Software-Based Self-Test programs for VLIW processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 20th Euromicro International Conference on Parallel, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012
2011
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.
IEEE Trans. Ind. Electron., 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011
Springer, ISBN: 978-1-4419-7594-2, 2011
2010
ACM Trans. Reconfigurable Technol. Syst., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
A novel scalable and reconfigurable emulation platform for embedded systems verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Lecture Notes in Electrical Engineering 26, Springer, ISBN: 978-1-4020-8978-7, 2009
IEEE Trans. Instrum. Meas., 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Reconfigurable Computing: Architectures, 2009
2008
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008
J. Electron. Test., 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008
A new placement algorithm for the optimization of fault tolerant circuits on reconfigurable devices.
Proceedings of the 5th Conference on Computing Frontiers, 2008
Differential gene expression graphs: A data structure for classification in DNA microarrays.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008
A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electron. Test., 2007
Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007
An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
IEEE Trans. Computers, 2006
J. Comput., 2006
A Fault Injection Environment for SoPC's Embedded Microprocessors.
Proceedings of the 7th Latin American Test Workshop, 2006
Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006
ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
New evolutionary techniques for test-program generation for complex microprocessor cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005
Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.
Proceedings of the 10th European Test Symposium, 2005
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005
Proceedings of the 2005 Design, 2005
2004
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004