Luca Sterpone

According to our database1, Luca Sterpone authored at least 126 papers between 2004 and 2019.

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2019
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs.
Integration, 2019

A new Method for the Analysis of Radiation-induced Effects in 3D VLSI Face-to-Back LUTs.
Proceedings of the 16th International Conference on Synthesis, 2019

On the evaluation of SEU effects in GPGPUs.
Proceedings of the IEEE Latin American Test Symposium, 2019

Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

On the Evaluation of the PIPB Effect within SRAM-based FPGAs.
Proceedings of the 24th IEEE European Test Symposium, 2019

Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks.
Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

On the Estimation of Complex Circuits Functional Failure Rate by Machine Learning Techniques.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2019

A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution Network.
Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

ReM: A Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018
OLT(RE)2: An On-Line On-Demand Testing Approach for Permanent Radiation Effects in Reconfigurable Systems.
IEEE Trans. Emerging Topics Comput., 2018

On the analysis of radiation-induced Single Event Transients on SRAM-based FPGAs.
Microelectronics Reliability, 2018

SETA: A CAD Tool for Single Event Transient Analysis and Mitigation on Flash-Based FPGAs.
Proceedings of the 15th International Conference on Synthesis, 2018

PyXEL: An Integrated Environment for the Analysis of Fault Effects in SRAM-Based FPGA Routing.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018

IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

About the functional test of the GPGPU scheduler.
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

On the mitigation of single event transients on flash-based FPGAs.
Proceedings of the 23rd IEEE European Test Symposium, 2018

MATS**: An On-Line Testing Approach for Reconfigurable Embedded Memories.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

Fast Partial Reconfiguration on SRAM-Based FPGAs: A Frame-Driven Routing Approach.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

A Novel Error Rate Estimation Approach forUltraScale+ SRAM-based FPGAs.
Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers, 2017

A new approach for Total Ionizing Dose effect analysis on Flash-based FPGA.
Microelectronics Reliability, 2017

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectronics Reliability, 2017

A probe-based SEU detection method for SRAM-based FPGAs.
Microelectronics Reliability, 2017

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
Journal of Systems Architecture - Embedded Systems Design, 2017

Evaluation of transient errors in GPGPUs for safety critical applications: An effective simulation-based fault injection environment.
Journal of Systems Architecture - Embedded Systems Design, 2017

Fault tolerant electronic system design.
Proceedings of the IEEE International Test Conference, 2017

Micro Latch-Up Analysis on Ultra-Nanometer VLSI Technologies: A New Monte Carlo Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Reliability evaluation of heterogeneous systems-on-chip for automotive ECUs.
Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

Analysis of radiation-induced cross domain errors in TMR architectures on SRAM-based FPGAs.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Online monitoring soft errors in reconfigurable FPGA during radiation test.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017

Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Self rerouting of dynamically reconfigurable SRAM-based FPGAs.
Proceedings of the 2017 NASA/ESA Conference on Adaptive Hardware and Systems, 2017

2016
Online Test of Control Flow Errors: A New Debug Interface-Based Approach.
IEEE Trans. Computers, 2016

On the prediction of radiation-induced SETs in flash-based FPGAs.
Microelectronics Reliability, 2016

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs.
Integration, 2016

An FPGA-based testing platform for the validation of automotive powertrain ECU.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Analysis of radiation-induced SEUs on dynamic reconfigurable systems.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

Hybrid soft error mitigation techniques for COTS processor-based systems.
Proceedings of the 17th Latin-American Test Symposium, 2016

Scalable FPGA graph model to detect routing faults.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A new EDA flow for the mitigation of SEUs in dynamic reconfigurable FPGAs.
Proceedings of the 21th IEEE European Test Symposium, 2016

A New Simulation-Based Fault Injection Approach for the Evaluation of Transient Errors in GPGPUs.
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016

2015
Radiation-induced single event transients modeling and testing on nanometric flash-based technologies.
Microelectronics Reliability, 2015

On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors.
IEEE Trans. VLSI Syst., 2014

ASSESS: A Simulator of Soft Errors in the Configuration Memory of SRAM-Based FPGAs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Evaluating the radiation sensitivity of GPGPU caches: New algorithms and experimental results.
Microelectronics Reliability, 2014

Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.
J. Electronic Testing, 2014

Soft error effects analysis and mitigation in VLIW safety-critical applications.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

A new solution to on-line detection of Control Flow Errors.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Validation of a tool for estimating the effects of soft-errors on modern SRAM-based FPGAs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Fault injection in GPGPU cores to validate and debug robust parallel applications.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Analysis and mitigation of single event effects on flash-based FPGAS.
Proceedings of the 19th IEEE European Test Symposium, 2014

Reconfigurable high performance architectures: How much are they ready for safety-critical applications?
Proceedings of the 19th IEEE European Test Symposium, 2014

Fault injection and fault tolerance methodologies for assessing device robustness and mitigating against ionizing radiation.
Proceedings of the 19th IEEE European Test Symposium, 2014

2013
A Novel Fault Tolerant and Runtime Reconfigurable Platform for Satellite Payload Processing.
IEEE Trans. Computers, 2013

SEL-UP: A CAD tool for the sensitivity analysis of radiation-induced Single Event Latch-Up.
Microelectronics Reliability, 2013

Partition-Based Faults Diagnosis of a VLIW Processor.
Proceedings of the VLSI-SoC: At the Crossroads of Emerging Trends, 2013

On the development of diagnostic test programs for VLIW processors.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Exploiting the debug interface to support on-line test of control flow errors.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

On the evaluation of soft-errors detection techniques for GPGPUs.
Proceedings of the 8th International Design and Test Symposium, 2013

Validation and robustness assessment of an automotive system.
Proceedings of the 8th International Design and Test Symposium, 2013

Unexcitability analysis of SEus affecting the routing structure of SRAM-based FPGAs.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

An error-detection and self-repairing method for dynamically and partially reconfigurable systems.
Proceedings of the 18th IEEE European Test Symposium, 2013

On-line testing of permanent radiation effects in reconfigurable systems.
Proceedings of the Design, Automation and Test in Europe, 2013

On the optimal reconfiguration times for TMR circuits on SRAM based FPGAs.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

Preface.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013

2012
On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors.
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

On the optimized generation of Software-Based Self-Test programs for VLIW processors.
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

A New Fault Injection Approach for Testing Network-on-Chips.
Proceedings of the 20th Euromicro International Conference on Parallel, 2012

On the development of Software-Based Self-Test methods for VLIW processors.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Accurate simulation of SEUs in the configuration memory of SRAM-based FPGAs.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A new SBST algorithm for testing the register file of VLIW processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A scalable platform for run-time reconfigurable satellite payload processing.
Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011
Coping With the Obsolescence of Safety- or Mission-Critical Embedded Systems Using FPGAs.
IEEE Trans. Industrial Electronics, 2011

A Low-Cost Emulation System for Fast Co-verification and Debug.
Proceedings of the 16th European Test Symposium, 2011

Fault injection analysis of transient faults in clustered VLIW processors.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

A new reconfigurable clock-gating technique for low power SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2011

Analysis of SEU effects in partially reconfigurable SoPCs.
Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, 2011

Reconfigurable Field Programmable Gate Arrays for Mission-Critical Applications.
Springer, ISBN: 978-1-4419-7594-2, 2011

2010
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs.
TRETS, 2010

A new software tool for static analysis of SET sensitiveness in Flash-based FPGAs.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

A novel scalable and reconfigurable emulation platform for embedded systems verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

An integrated flow for the design of hardened circuits on SRAM-based FPGAs.
Proceedings of the 15th European Test Symposium, 2010

A New Soft-Error Resilient Voltage-Mode Quaternary Latch.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

On the mitigation of SET broadening effects in integrated circuits.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Electronics System Design Techniques for Safety Critical Applications
Lecture Notes in Electrical Engineering 26, Springer, ISBN: 978-1-4020-8978-7, 2009

A Novel Dual-Core Architecture for the Analysis of DNA Microarray Images.
IEEE Trans. Instrumentation and Measurement, 2009

A new RC design for mixed-grain based dynamically reconfigurable architectures.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

Soft errors in Flash-based FPGAs: Analysis methodologies and first results.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

A study of the Single Event Effects impact on functional mapping within Flash-based FPGAs.
Proceedings of the Design, Automation and Test in Europe, 2009

Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, 2009

2008
FPGA PAL Design Tools.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

Software and Hardware Techniques for SEU Detection in IP Processors.
J. Electronic Testing, 2008

On the Evaluation of Radiation-Induced Transient Faults in Flash-Based FPGAs.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On the design of tunable fault tolerant circuits on SRAM-based FPGAs for safety critical applications.
Proceedings of the Design, Automation and Test in Europe, 2008

A graph-based representation of Gene Expression profiles in DNA microarrays.
Proceedings of the 2008 IEEE Symposium on Computational Intelligence in Bioinformatics and Computational Biology, 2008

Differential gene expression graphs: A data structure for classification in DNA microarrays.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008

A Novel Design Flow for the Performance Optimization of Fault Tolerant Circuits on SRAM-based FPGA's.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs.
J. Electronic Testing, 2007

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
CoRR, 2007

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A new hardware architecture for performing the gridding of DNA microarray images.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

A new decompression system for the configuration process of SRAM-based FPGAS.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs.
Proceedings of the 12th European Test Symposium, 2007

Optimization of Self Checking FIR filters by means of Fault Injection Analysis.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAs.
Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs.
IEEE Trans. Computers, 2006

Hardening FPGA-based Systems Against SEUs: A New Design Methodology.
JCP, 2006

Dependability Evaluation of Transient Fault Effects in Reconfigurable Compute Fabric Devices.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Fault Injection-based Reliability Evaluation of SoPCs.
Proceedings of the 11th European Test Symposium, 2006

Combined software and hardware techniques for the design of reliable IP processors.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

ReCoM: A New Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A new approach to compress the configuration information of programmable devices.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

2005
Efficient Estimation of SEU Effects in SRAM-Based FPGAs.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

New evolutionary techniques for test-program generation for complex microprocessor cores.
Proceedings of the Genetic and Evolutionary Computation Conference, 2005

Multiple errors produced by single upsets in FPGA configuration memory: a possible solution.
Proceedings of the 10th European Test Symposium, ETS 2005, Tallinn, 2005

A design flow for protecting FPGA-based systems against single event upsets.
Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs.
Proceedings of the 2005 Design, 2005

2004
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004


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