Anees Ullah
Orcid: 0000-0002-4770-4967
According to our database1,
Anees Ullah
authored at least 29 papers
between 2012 and 2023.
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Bibliography
2023
Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023
ACM Trans. Embed. Comput. Syst., July, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2023
AVPCD: a plant-derived medicine database of antiviral phytochemicals for cancer, Covid-19, malaria and HIV.
Database J. Biol. Databases Curation, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Fault Tolerant Polyphase Filters-Based Decimators for SRAM-Based FPGA Implementations.
IEEE Trans. Emerg. Top. Comput., 2022
IEEE Embed. Syst. Lett., 2022
2021
Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Towards Low Latency and Resource-Efficient FPGA Implementations of the MUSIC Algorithm for Direction of Arrival Estimation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Intelligent Energy-Based Modified Super Twisting Algorithm and Factional Order PID Control for Performance Improvement of PMSG Dedicated to Tidal Power System.
IEEE Access, 2021
2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
Proceedings of the 2020 IEEE Conference on Network Function Virtualization and Software Defined Networks, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
2018
Efficient Protection of the Register File in Soft-Processors Implemented on Xilinx FPGAs.
IEEE Trans. Computers, 2018
Multiple Hash Matching Units (MHMU): An Algorithmic Ternary Content Addressable Memory Design for Field Programmable Gate Arrays.
Proceedings of the IEEE 19th International Conference on High Performance Switching and Routing, 2018
2017
An Error-Detection and Self-Repairing Method for Dynamically and Partially Reconfigurable Systems.
IEEE Trans. Computers, 2017
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab., 2017
A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
J. Syst. Archit., 2017
Improving the Hardware Complexity by Exploiting the Reduced Dynamics-Based Fractional Order Systems.
IEEE Access, 2017
2015
PhD thesis, 2015
2014
Recovery Time and Fault Tolerance Improvement for Circuits mapped on SRAM-based FPGAs.
J. Electron. Test., 2014
Effective emulation of permanent faults in ASICs through dynamically reconfigurable FPGAs.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
Dynamic neutron testing of Dynamically Reconfigurable Processing Modules architecture.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
Comparison Based Analysis of Different Cryptographic and Encryption Techniques Using Message Authentication Code (MAC) in Wireless Sensor Networks (WSN).
CoRR, 2012