Luis Peña Treviño

According to our database, Luis Peña Treviño authored at least 6 papers between 2023 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Exploiting Timing-Power Causality for Post-Route Metric Prediction via Hierarchical Learning.

Luis Peña Treviño, Eric Guerra Ribeiro, Lirida Naviner, Fady Abouzeid, Philippe Roche

Proceedings of the 17th IEEE Latin America Symposium on Circuits and System, 2026

Multi-Node Timing and Power Estimation with Adapter-Based Transfer Learning.

Luis Peña Treviño, Eric Guerra Ribeiro, Lirida A. B. Naviner, Fady Abouzeid, Philippe Roche

Proceedings of the 27th International Symposium on Quality Electronic Design, 2026

2025

Approximate Analytical Model Evaluating Digital Systems Compliance with Automotive Standards.

Esther Goudet, Fabio Sureau, Manan Kaila, Rémi Germe, Luis Peña Treviño, Jean-Marc Daveau, Lirida Naviner, Philippe Roche

Proceedings of the 26th IEEE Latin American Test Symposium, 2025

2024

Analysis of Combinational Circuit Failure Rate based on Graph Partitioning and Probabilistic Binomial Approach.

Esther Goudet, Fabio Sureau, Paul Breuil, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche

J. Electron. Test., June, 2024

Drift of Combinational Circuits Failure Rates with a Probabilistic Model Approximated by Partitioning.

Esther Goudet, Luis Peña Treviño, Gutemberg G. dos Santos Júnior, Sayah El Hajji, Fabio Sureau, Lirida Naviner, Jean-Marc Daveau, Philippe Roche

Proceedings of the 37th SBC/SBMicro/IEEE Symposium on Integrated Circuits and Systems Design, 2024

2023

Fast analysis of combinatorial netlists correctness rate based on binomial law and partitioning.

Esther Goudet, Luis Peña Treviño, Lirida A. B. Naviner, Jean-Marc Daveau, Philippe Roche

Proceedings of the 24th IEEE Latin American Test Symposium, 2023