Jean-Marc Daveau

According to our database1, Jean-Marc Daveau authored at least 26 papers between 1995 and 2021.

Collaborative distances:



In proceedings 
PhD thesis 




Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

FIRECAP: Fail-Reason Capturing hardware module for a RISC-V based System on a Chip.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2018

A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

30% static power improvement on ARM Cortex<sup>®</sup>-A53 using static biasing-anticipation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

Partial triplication of a SPARC-V8 microprocessor using fault injection.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.
Proceedings of the ESSCIRC Conference 2015, 2015

An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Fast reliability analysis of combinatorial logic circuits using conditional probabilities.
Microelectron. Reliab., 2010

Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Verification of soft error detection mechanism through fault injection on hardware emulation platform.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A retargetable register allocation framework for embedded processors.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

FlexCC2: An Optimizing Retargetable C Compiler for DSP Processors.
Proceedings of the Embedded Software, Second International Conference, 2002

Automating the Design of SOCs Using Cores.
IEEE Des. Test Comput., 2001

Interlanguage Communication Synthesis for Heterogeneous Specifications.
Des. Autom. Embed. Syst., 2000

Communication Interface Synthesis for Multilanguage Specifications.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999

Hardware/Software Co-Design Methodology for Design of Embedded Systems.
Integr. Comput. Aided Eng., 1998

Hardware/software co-design of an ATM network interface card: a case study.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998

Protocol selection and interface generation for HW-SW codesign.
IEEE Trans. Very Large Scale Integr. Syst., 1997

Transformational partitioning for co-design of multiprocessor systems.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

A system-level communication synthesis approach for hardware/software systems.
Microprocess. Microsystems, 1996

Synthesis of system-level communication by an allocation-based approach.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995