Philippe Roche

According to our database1, Philippe Roche authored at least 40 papers between 2006 and 2019.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
CovaDOTS: In Silico Chemistry-Driven Tool to Design Covalent Inhibitors Using a Linking Strategy.
J. Chem. Inf. Model., 2019

2018
A 2.7 pJ/cycle 16 MHz, 0.7 µW Deep Sleep Power ARM Cortex-M0+ Core SoC in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2018

Q-Learning-based Adaptive Power Management for IoT System-on-Chips with Embedded Power States.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 140 nW, 32.768 kHz, 1.9 ppm/°C Leakage-Based Digitally Relocked Clock Reference with 0.1 ppm Long-Term Stability in 28nm FD-SOI.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
Multi-Poisson process analysis of real-time soft-error rate measurements in bulk 65 nm and 40 nm SRAMs.
Microelectron. Reliab., 2017

A 2.7pJ/cycle 16MHz SoC with 4.3nW power-off ARM Cortex-M0+ core in 28nm FD-SOI.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017

A 0.40pJ/cycle 981 μm<sup>2</sup> voltage scalable digital frequency generator for SoC clocking.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
2P2Idb v2: update of a structural database dedicated to orthosteric modulation of protein-protein interactions.
Database J. Biol. Databases Curation, 2016

A 28nm FD-SOI standard cell 0.6-1.2V open-loop frequency multiplier for low power SoC clocking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

30% static power improvement on ARM Cortex<sup>®</sup>-A53 using static biasing-anticipation.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
ASTEP (2005-2015): Ten years of soft error and atmospheric radiation characterization on the Plateau de Bure.
Microelectron. Reliab., 2015

Partial triplication of a SPARC-V8 microprocessor using fault injection.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Alpha soft error rate of FDSOI 28 nm SRAMs: Experimental testing and simulation analysis.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Muons and thermal neutrons SEU characterization of 28nm UTBB FD-SOI and Bulk eSRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Frequency and voltage effects on SER on a 65nm Sparc-V8 microprocessor under radiation test.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

28nm FD-SOI technology and design platform for sub-10pJ/cycle and SER-immune 32bits processors.
Proceedings of the ESSCIRC Conference 2015, 2015

2014
Real-time soft-error rate measurements: A review.
Microelectron. Reliab., 2014

Particle Monte Carlo modeling of single-event transient current and charge collection in integrated circuits.
Microelectron. Reliab., 2014

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI.
IEEE J. Solid State Circuits, 2014


2013
2P2Idb: a structural database dedicated to orthosteric modulation of protein-protein interactions.
Nucleic Acids Res., 2013


2012
A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance.
Proceedings of the IEEE International Conference on IC Design & Technology, 2012

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance.
Proceedings of the 38th European Solid-State Circuit conference, 2012

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
An approach to reduce computational cost in combinatorial logic netlist reliability analysis using circuit clustering and conditional probabilities.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

A 240mV 1MHz, 340mV 10MHz, 40nm CMOS, 252 bits frame decoder using ultra-low voltage circuit design platform.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Fast reliability analysis of combinatorial logic circuits using conditional probabilities.
Microelectron. Reliab., 2010

Soft-errors induced by terrestrial neutrons and natural alpha-particle emitters in advanced memory circuits at ground level.
Microelectron. Reliab., 2010

Handling reconvergent paths using conditional probabilities in combinatorial logic netlist reliability estimation.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Verification of soft error detection mechanism through fault injection on hardware emulation platform.
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010

2008
A Radiation Hardened Nano-Power 8Mb SRAM in 130nm CMOS.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Growing Interest of Advanced Commercial CMOS Technologies for Space and Medical Applications. Illustration with a New Nano-Power and Radiation-Hardened SRAM in 130nm CMOS.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Factors That Impact the Critical Charge of Memory Elements.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

A Flexible SoPC-based Fault Injection Environment.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006


  Loading...