Ma José Canet

Orcid: 0000-0002-6765-9219

According to our database1, Ma José Canet authored at least 28 papers between 2003 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2023
Model and Methodology to Characterize Phosphor-Based White LED Visible Light Communication Links.
Sensors, 2023

2021
Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications.
Sensors, 2021

2019
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2016
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2016

High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
A 630 Mbps non-binary LDPC decoder for FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.
Circuits Syst. Signal Process., 2013

High-speed NB-LDPC decoder for wireless applications.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

2012
Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles.
J. Signal Process. Syst., 2012

Improved Sliced Message Passing Architecture for High Throughput Decoding of LDPC Codes.
J. Signal Process. Syst., 2012

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012

FPGA implementation of an OFDM-based WLAN receiver.
Microprocess. Microsystems, 2012

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.
IEEE Commun. Lett., 2012

Decoder for an enhanced serial generalized bit flipping algorithm.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2009
Power Consumption Reduction in a Viterbi Decoder for OFDM-WLAN.
J. Circuits Syst. Comput., 2009

2008
Architectures for the Implementation of a OFDM-WLAN Viterbi Decoder.
J. Signal Process. Syst., 2008

Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN.
J. Signal Process. Syst., 2008

64-QAM 4×4 MIMO decoders based on Successive Projection Algorithm.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Time Synchronization for the IEEE 802.11a/g WLAN Standard.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Reduction of power consumption in a Viterbi Decoder for OFDM-WLAN.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Improvement of a time synchronization algorithm for IEEE 802.11a/g WLAN standard.
Proceedings of the 15th European Signal Processing Conference, 2007

2005
Performance evaluation of fine time synchronizers for WLANs.
Proceedings of the 13th European Signal Processing Conference, 2005

2004
A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems.
Proceedings of the IEEE 15th International Symposium on Personal, 2004

Analysis and Contrast Between STC and Spatial Diversity Techniques for OFDM WLAN with Channel Estimation.
Proceedings of the Telecommunications and Networking, 2004

Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2.
Proceedings of the Field Programmable Logic and Application, 2004

2003
DIGIMOD: A Tool to Implement FPGA-Based Digital IF and Baseband Modems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003


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