Francisco Garcia-Herrero

Orcid: 0000-0001-6719-9681

Affiliations:
  • Complutense University of Madrid, Spain


According to our database1, Francisco Garcia-Herrero authored at least 41 papers between 2011 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
Integration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension.
IEEE Trans. Aerosp. Electron. Syst., October, 2023

RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography.
IEEE Trans. Computers, March, 2023

Low-Complexity Linear Programming Based Decoding of Quantum LDPC codes.
CoRR, 2023

Layered Decoding of Quantum LDPC Codes.
Proceedings of the 12th International Symposium on Topics in Coding, 2023

2022
Design and implementation of efficient QCA full-adders using fault-tolerant majority gates.
J. Supercomput., 2022

Reducing the Impact of Defects in Quantum-Dot Cellular Automata (QCA) Approximate Adders at Nano Scale.
IEEE Trans. Emerg. Top. Comput., 2022

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

Flexible and area-efficient Galois field Arithmetic Logic Unit for soft-core processors.
Comput. Electr. Eng., 2022

2021
Combined Symbol Error Correction and Spare Through-Silicon Vias for 3D Memories.
IEEE Trans. Emerg. Top. Comput., 2021

Decoding Algorithm for Quadruple-Error-Correcting Reed-Solomon Codes and Its Derived Architectures.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial.
Sensors, 2021

Low delay non-binary error correction codes based on Orthogonal Latin Squares.
Integr., 2021

Syndrome-Based Min-Sum vs OSD-0 Decoders: FPGA Implementation and Analysis for Quantum LDPC Codes.
IEEE Access, 2021

Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs.
IEEE Access, 2021

Project-Based Learning with historic buildings: immersion in real training environments for the Degree in Technical Architecture.
Proceedings of the International Conference of Innovation, 2021

2020
Low-Latency and Low-Power Test-Vector Selector for Reed-Solomon's Low-Complexity Chase.
IEEE Trans. Circuits Syst., 2020

Two Behavioural Error Detection Techniques for the Cascaded Integrator-Comb Interpolation Filter Implemented on FPGA.
Circuits Syst. Signal Process., 2020

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications.
IEEE Access, 2020

2019
A Test Vector Generation Method Based on Symbol Error Probabilities for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Reed-Solomon Decoder Based on a Modified ePIBMA for Low-Latency 100 Gbps Communication Systems.
Circuits Syst. Signal Process., 2019

Second Minimum Approximation for Min-Sum Decoders Suitable for High-Rate LDPC Codes.
Circuits Syst. Signal Process., 2019

2018
Soft-decision LCC Decoder Architecture with n=4 for RS(255, 239).
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

High-Throughput One-Channel RS(255, 239) Decoder.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2016
Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2016

High-Performance NB-LDPC Decoder With Reduction of Message Exchange.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Reduction of Complexity for Nonbinary LDPC Decoders With Compressed Messages.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Simplified Trellis Min-Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2015

One Minimum Only Trellis Decoder for Non-Binary Low-Density Parity-Check Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A 630 Mbps non-binary LDPC decoder for FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Multiple-Vote Symbol-Flipping Decoder for Nonbinary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Non-Binary LDPC Decoder Based on Symbol Flipping with Multiple Votes.
IEEE Commun. Lett., 2014

Reliability-Based Iterative Decoding Algorithm for LDPC Codes With Low Variable-Node Degree.
IEEE Commun. Lett., 2014

A symbol flipping decoder for NB-LDPC relying on multiple votes.
Proceedings of the 8th International Symposium on Turbo Codes and Iterative Information Processing, 2014

2013
Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes.
Circuits Syst. Signal Process., 2013

High-speed NB-LDPC decoder for wireless applications.
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2013

Low latency T-EMS decoder for non-binary LDPC codes.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.
IEEE Commun. Lett., 2012

Decoder for an enhanced serial generalized bit flipping algorithm.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
High-Speed RS(255, 239) Decoder Based on LCC Decoding.
Circuits Syst. Signal Process., 2011


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